and 16-Bit, 250-MSPS ADC

76 Pages·2014·5.2 MB·English

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ADS42JB49,ADS42JB69
SLAS900F–OCTOBER2012–REVISEDDECEMBER2014
ADS42JBx9 Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters
1 Features 2 Applications
• Dual-ChannelADCs • CommunicationandCableInfrastructure
1
• 14-and16-BitResolution • Multi-Carrier,MultimodeCellularReceivers
• MaximumClockRate:250MSPS • Radar andSmartAntennaArrays
• JESD204BSerial Interface • BroadbandWireless
– Subclass0,1,2Compliant • TestandMeasurementSystems
– Upto3.125Gbps • Software-DefinedandDiversityRadios
– TwoandFourLanesSupport • MicrowaveandDual-ChannelI/QReceivers
• AnalogInputBufferwithHigh-ImpedanceInput • Repeaters
• FlexibleInputClockBuffer: • PowerAmplifierLinearization
Divide-by-1,-2,and-4
3 Description
• DifferentialFull-ScaleInput:2V and2.5V
PP PP
(RegisterProgrammable) The ADS42JB69 and ADS42JB49 are high-linearity,
dual-channel, 16- and 14-bit, 250-MSPS, analog-to-
• Package:9-mm×9-mmVQFN-64
digital converters (ADCs). These devices support the
• PowerDissipation:850mW/Ch JESD204B serial interface with data rates up to
• ApertureJitter:85f rms 3.125 Gbps. The buffered analog input provides
S
uniform input impedance across a wide frequency
• InternalDither
range while minimizing sample-and-hold glitch energy
• ChannelIsolation:100dB
making it easy to drive analog inputs up to very high
• Performance: input frequencies. A sampling clock divider allows
– f =170MHzat2V , –1dBFS more flexibility for system clock architecture design.
IN PP
The devices employ internal dither algorithms to
– SNR: 73.3dBFS
provide excellent spurious-free dynamic range
– SFDR:93dBcforHD2,HD3 (SFDR) overalargeinput frequencyrange.
– SFDR:100dBcforNonHD2,HD3
DeviceInformation(1)
– f =170MHzat2.5V , –1dBFS
IN PP
PARTNUMBER PACKAGE INTERFACEOPTION
– SNR: 74.7dBFS
14-bitDDRorQDRLVDS
– SFDR:89dBcforHD2,HD3and ADS42JB49 VQFN(64)
14-bitJESD204B
95dBcforNonHD2,HD3
16-bitDDRorQDRLVDS
ADS42JB69 VQFN(64)
16-bitJESD204B
(1) For all available packages, see the orderable addendum at
theendofthedatasheet.
space
space
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.
ADS42JB49,ADS42JB69
SLAS900F–OCTOBER2012–REVISEDDECEMBER2014 www.ti.com
SimplifiedSchematic
Device Digital OVRA FFTfor170MHzInputSignal
IINNAAMP, 14-A, D16C-Bit TesBGt lMoacionkdes JEDSiDg2ita0l4B DDDDAAAA1010PPMM,, 0 FFisn==215700MMsHpsz
-20 Ain=-1dBFS
CLKINP, Divide PLL
CLKINM by1, 2,4 x10, x20 SYNC~P, HD2=90dBc
SYNC~M HD3=89dBc
SSYYSSRREEFFMP, Delay -40 NonHD2,3=100dBc
IINNBBMP, 14-A, D16C-Bit TesDBGt ilMgoaicitonakdles JEDSiDg2ita0l4B DDODDBBBBV1100RPMMPB,, mplitude(dB) -60
VCM CoMmomdeon Device Configuration A -80
RESETSENSCLKSDATASDOUTPDNPDN_GBLMODECTRL1CTRL2STBY -100
-120
0 25 50 75 100 125
Frequency(MHz)
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Table of Contents
1 Features.................................................................. 1 9.1 Overview.................................................................31
2 Applications........................................................... 1 9.2 FunctionalBlockDiagram.......................................31
3 Description............................................................. 1 9.3 FeatureDescription.................................................31
9.4 DeviceFunctionalModes........................................33
4 RevisionHistory..................................................... 3
9.5 Programming...........................................................39
5 DeviceComparisonTable..................................... 5
9.6 RegisterMaps.........................................................42
6 PinConfigurationandFunctions......................... 5
10 ApplicationandImplementation........................ 57
7 Specifications......................................................... 7
10.1 ApplicationInformation..........................................57
7.1 AbsoluteMaximumRatings......................................7
10.2 TypicalApplication................................................57
7.2 ESDRatings..............................................................7
11 PowerSupplyRecommendations..................... 63
7.3 RecommendedOperatingConditions.......................8
12 Layout................................................................... 63
7.4 ThermalInformation..................................................8
12.1 LayoutGuidelines.................................................63
7.5 ElectricalCharacteristics:ADS42JB69(16-Bit)........9
12.2 LayoutExample....................................................65
7.6 ElectricalCharacteristics:ADS42JB49(14-Bit)......10
13 DeviceandDocumentationSupport................. 66
7.7 ElectricalCharacteristics:General..........................11
7.8 DigitalCharacteristics.............................................12 13.1 DeviceSupport......................................................66
7.9 TimingCharacteristics.............................................13 13.2 DocumentationSupport........................................68
7.10 TypicalCharacteristics:ADS42JB69....................15 13.3 RelatedLinks........................................................68
7.11 TypicalCharacteristics:ADS42JB49....................20 13.4 Trademarks...........................................................68
7.12 TypicalCharacteristics:Common.........................25 13.5 ElectrostaticDischargeCaution............................68
7.13 TypicalCharacteristics:Contour...........................26 13.6 Glossary................................................................68
8 ParameterMeasurementInformation................29 14 Mechanical,Packaging,andOrderable
Information........................................................... 68
9 DetailedDescription............................................ 31
4 Revision History
NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion.
ChangesfromRevisionE(August2013)toRevisionF Page
• Changedformattomeetlatestdatasheetstandards............................................................................................................ 1
• AddedESDRatingstableandFeatureDescription,DeviceFunctionalModes,Applicationand
Implementation,PowerSupplyRecommendations,Layout,DeviceandDocumentationSupport,andMechanical,
Packaging,andOrderableInformationsections..................................................................................................................... 1
• ChangedtitleofDeviceComparisonTable............................................................................................................................ 5
• ChangedtitleofPinFunctionstable....................................................................................................................................... 6
• DeletedOrderingInformationtable........................................................................................................................................ 7
• Correctednamesofregisters10h,11h,12h,and13hinTable13 ..................................................................................... 42
ChangesfromRevisionD(August2013)toRevisionE Page
• ChangeddocumentstatustoProductionData....................................................................................................................... 1
ChangesfromRevisionC(July2013)toRevisionD Page
• Updatedfrontpageblockdiagram......................................................................................................................................... 2
• Changed2-V Full-ScaleINLmaximumspecificationinADS42JB49ElectricalCharacteristicstable.............................. 10
PP
ChangesfromRevisionB(July2013)toRevisionC Page
• AddedInternalDitherinFeaturesSection............................................................................................................................. 1
• ChangedFrom"Thedevicesprovideexcellent"to"Thedevicesemployinternalditheralgorithmstoprovide"................... 1
• Changed2-V Full-ScaleINLmaximumspecificationinADS42JB69ElectricalCharacteristicstable................................ 9
PP
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• Deleted2.5-V Full-ScaleINLmaximumspecificationinADS42JB69ElectricalCharacteristicstable............................... 9
PP
• Changed2-V Full-ScaleINLmaximumspecificationinADS42JB49ElectricalCharacteristicstable.............................. 10
PP
• Deleted2.5-V Full-ScaleINLmaximumspecificationinADS42JB49ElectricalCharacteristicstable............................. 10
PP
• ChangedE specificationsinGeneralElectricalCharacteristicstable........................................................................... 11
GREF
ChangesfromRevisionA(November2012)toRevisionB Page
• ChangeddocumentstatustoMixedStatus............................................................................................................................ 1
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5 Device Comparison Table
14-BIT, 14-BIT, 16-BIT,
INTERFACEOPTION
160MSPS 250MSPS 250MSPS
DDRorQDRLVDS — ADS42LB49 ADS42LB69
JESD204B ADS42JB46 ADS42JB49 ADS42JB69
6 Pin Configuration and Functions
RGCPackage
VQFN-64
(TopView)
DRVDD DGND OVRB OVRA DRVDD DB1M DB1P DB0M DB0P OVDD DA0P DA0M DA1P DA1M DGND DRVDD
I
4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9
6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4
DGND 1 48 DGND
DRVDD 2 47 DRVDD
DGND 3 46 DGND
MODE 4 45 SDOUT
STBY 5 44 RESET
PDN_GBL 6 43 SCLK
DRVDD 7 42 SDATA
SYNC~M 8 Thermal Pad 41 SEN
SYNC~P 9 40 AVDD
CTRL2 10 39 CTRL1
AVDD 11 38 AVDD
AGND 12 37 AGND
INBP 13 36 INAP
INBM 14 35 INAM
AGND 15 34 AGND
AVDD 16 33 AVDD
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
V D D D M D D M P D D D P M D V
AVDD3 AVD AGN AGN VC AVD AGN CLKIN CLKIN AGN AVD AGN YSREF YSREF AVD AVDD3
S S
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PinFunctions: JESD204BOutput Interface
PIN
DESCRIPTION
NAME NO. I/O FUNCTION
12,15,19,20,
AGND 23,26,28,34, I Supply Analogground
37
11,16,18,22,
AVDD 27,31,33,38, I Supply 1.8-Vanalogpowersupply
40
AVDD3V 17,32 I Supply 3.3-Vanalogsupplyforanalogbuffer
CLKINM 24 I Clock DifferentialADCclockinput
CLKINP 25 I Clock DifferentialADCclockinput
CTRL1 39 I Control Power-downcontrolwithaninternal150-kΩpull-downresistor
CTRL2 10 I Control Power-downcontrolwithaninternal150-kΩpull-downresistor
DA0P/M 54,53 O Interface JESD204BserialdataoutputforchannelA,lane0
DA1P/M 52,51 O Interface JESD204BserialdataoutputforchannelA,lane1
DB0P/M 56,57 O Interface JESD204BserialdataoutputforchannelB,lane0
DB1P/M 58,59 O Interface JESD204BserialdataoutputforchannelB,lane1
1,3,46,48,
DGND I Supply Digitalground
50,63
2,7,47,49,
DRVDD I Supply Digital1.8-Vpowersupply
60,64
INAM 35 I Input DifferentialanaloginputforchannelA
INAP 36 I Input DifferentialanaloginputforchannelA
INBM 14 I Input DifferentialanaloginputforchannelB
INBP 13 I Input DifferentialanaloginputforchannelB
IOVDD 55 I Supply Digital1.8-VpowersupplyfortheJESD204Btransmitter
MODE 4 I Control ConnecttoGND
OVRA 61 O Interface OverrangeindicationchannelAinCMOSoutputformat.
OVRB 62 O Interface OverrangeindicationchannelBinCMOSoutputformat.
PDN_GBL 6 I Control Globalpowerdown.Activehighwithaninternal150-kΩpull-downresistor.
RESET 44 I Control Hardwarereset;activehigh.Thispinhasaninternal150-kΩpull-downresistor.
SCLK 43 I Control Serialinterfaceclockinput.Thispinhasaninternal150-kΩpull-downresistor.
SDATA 42 I Control Serialinterfacedatainput.Thispinhasaninternal150-kΩpull-downresistor.
SDOUT 45 O Control Serialinterfacedataoutput
SEN 41 I Control Serialinterfaceenable.Thispinhasaninternal150-kΩpull-upresistor.
STBY 5 I Control Standby.Activehighwithaninternal150-kΩpull-downresistor.
SYNC~P 9 I Interface SynchronizationinputforJESD204Bport
SYNC~M 8 I Interface SynchronizationinputforJESD204Bport
SYSREFM 30 I Clock ExternalSYSREFinput(subclass1)
SYSREFP 29 I Clock ExternalSYSREFinput(subclass1)
VCM 21 O Output 1.9-Vcommon-modeoutputvoltageforanaloginputs
Thermalpad — GND Ground Connecttogroundplane
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7 Specifications
7.1 Absolute Maximum Ratings
overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)
MIN MAX UNIT
AVDD3V –0.3 3.6 V
AVDD –0.3 2.1 V
Supplyvoltage
DRVDD –0.3 2.1 V
IOVDD –0.3 2.1 V
VoltagebetweenAGNDandDGND –0.3 0.3 V
INAP,INBP,INAM,INBM –0.3 3 V
CLKINP,CLKINM –0.3 minimum(2.1,AVDD+0.3) V
SYNC~P,SYNC~M –0.3 minimum(2.1,AVDD+0.3) V
Voltageappliedtoinputpins
SYSREFP,SYSREFM –0.3 minimum(2.1,AVDD+0.3) V
SCLK,SEN,SDATA,RESET,PDN_GBL,
–0.3 3.9 V
CTRL1,CTRL2,STBY,MODE
Operatingfree-air,T –40 +85 °C
A
Temperature Operatingjunction,T +125 °C
J
Storage,T –65 +150 °C
stg
(1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings
only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended
OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
7.2 ESD Ratings
VALUE UNIT
V Electrostaticdischarge Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V
(ESD)
(1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.
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7.3 Recommended Operating Conditions
overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)
MIN NOM MAX UNIT
SUPPLIES
AVDD Analogsupplyvoltage 1.7 1.8 1.9 V
AVDD3V Analogbuffersupplyvoltage 3.15 3.3 3.45 V
DRVDD Digitalsupplyvoltage 1.7 1.8 1.9 V
IOVDD Outputbuffersupplyvoltage 1.7 1.8 1.9 V
ANALOGINPUTS
Defaultafterreset 2 V
PP
V Differentialinputvoltagerange
ID Registerprogrammable(2) 2.5 V
PP
V Inputcommon-modevoltage VCM±0.025 V
ICR
Maximumanaloginputfrequencywith2.5-V inputamplitude 250 MHz
PP
Maximumanaloginputfrequencywith2-V inputamplitude 400 MHz
PP
CLOCKINPUT
10xmode 60 250 MSPS
Inputclocksamplerate
20xmode 40 156.25 MSPS
Sinewave,ac-coupled 0.3(3) 1.5 V
PP
Inputclockamplitudedifferential LVPECL,ac-coupled 1.6 VPP
(VCLKP–VCLKM) LVDS,ac-coupled 0.7 VPP
LVCMOS,single-ended,ac-coupled 1.5 V
Inputclockdutycycle 35% 50% 65%
DIGITALOUTPUTS
C MaximumexternalloadcapacitancefromeachoutputpintoDRGND 3.3 pF
LOAD
R Single-endedloadresistance +50 Ω
LOAD
T Operatingfree-airtemperature –40 +85 °C
A
(1) Afterpower-up,toresetthedeviceforthefirsttime,usetheRESETpinonly.RefertotheRegisterInitializationsection.
(2) Fordetails,refertotheDigitalGainsection.
(3) RefertothePerformancevsClockAmplitudecurves,Figure28andFigure29.
7.4 Thermal Information
ADS42JBx9
THERMALMETRIC(1) RGC(QFN) UNIT
64PINS
R Junction-to-ambientthermalresistance 22.9
θJA
R Junction-to-case(top)thermalresistance 7.1
θJC(top)
R Junction-to-boardthermalresistance 2.5
θJB
°C/W
ψ Junction-to-topcharacterizationparameter 0.1
JT
ψ Junction-to-boardcharacterizationparameter 2.5
JB
R Junction-to-case(bottom)thermalresistance 0.2
θJC(bot)
(1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953.
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7.5 Electrical Characteristics: ADS42JB69 (16-Bit)
TypicalvaluesareatT =+25°C,AVDD=1.8V,AVDD3V=3.3V,DRVDD=1.8V,IOVDD=1.8V,50%clockdutycycle,
A
–1-dBFSdifferentialanaloginput,andsamplingrate=250MSPS,unlessotherwisenoted.Minimumandmaximumvalues
areacrossthefulltemperaturerangeofT =–40°CtoT =+85°C,AVDD=1.8V,AVDD3V=3.3V,DRVDD=1.8V,
MIN MAX
andIOVDD=1.8V.
2-V FULL-SCALE 2.5-V FULL-SCALE
PP PP
PARAMETER TESTCONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
f =10MHz 74 75.9 dBFS
IN
f =70MHz 73.8 75.6 dBFS
IN
SNR Signal-to-noiseratio
f =170MHz 70.8 73.3 74.7 dBFS
IN
f =230MHz 72.6 74 dBFS
IN
f =10MHz 73.9 75.7 dBFS
IN
f =70MHz 73.7 75.3 dBFS
IN
SINAD Signal-to-noiseanddistortionratio
f =170MHz 69.6 73.2 74.5 dBFS
IN
f =230MHz 72.2 73.1 dBFS
IN
f =10MHz 95 90 dBc
IN
Spurious-freedynamicrange f =70MHz 91 88 dBc
IN
SFDR (includingsecondandthird
harmonicdistortion) fIN=170MHz 81 93 89 dBc
f =230MHz 84 82 dBc
IN
f =10MHz 92 88 dBc
IN
f =70MHz 89 86 dBc
IN
THD Totalharmonicdistortion
f =170MHz 78 91 86 dBc
IN
f =230MHz 82 80 dBc
IN
f =10MHz 95 95 dBc
IN
f =70MHz 91 88 dBc
IN
HD2 2nd-orderharmonicdistortion
f =170MHz 81 93 94 dBc
IN
f =230MHz 84 82 dBc
IN
f =10MHz 95 90 dBc
IN
f =70MHz 96 93 dBc
IN
HD3 3rd-orderharmonicdistortion
f =170MHz 81 94 89 dBc
IN
f =230MHz 86 84 dBc
IN
f =10MHz 102 102 dBc
IN
Worstspur f =70MHz 103 103 dBc
IN
(otherthansecondandthird
harmonics) fIN=170MHz 87 100 95 dBc
f =230MHz 99 93 dBc
IN
f =46MHz,f =50MHz,
1 2 97 95 dBFS
Two-toneintermodulation eachtoneat–7dBFS
IMD
distortion f =185MHz,f =190MHz,
1 2 90 89 dBFS
eachtoneat–7dBFS
20-MHz,full-scalesignalon
channelunderobservation;
Crosstalk 100 100 dB
170-MHz,full-scalesignalon
otherchannel
Recoverytowithin1%(offull-
Clock
Inputoverloadrecovery scale)for6-dBoverloadwithsine- 1 1
cycle
waveinput
For50-mV signalonAVDD
PSRR ACpower-supplyrejectionratio PP >40 >40 dB
supply,upto10MHz
ENOB Effectivenumberofbits f =170MHz 11.9 12.1 LSBs
IN
DNL Differentialnonlinearity f =170MHz ±0.6 ±0.6 LSBs
IN
INL Integratednonlinearity f =170MHz ±3 ±8 ±3.5 LSBs
IN
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7.6 Electrical Characteristics: ADS42JB49 (14-Bit)
TypicalvaluesareatT =+25°C,AVDD=1.8V,AVDD3V=3.3V,DRVDD=1.8V,IOVDD=1.8V,50%clockdutycycle,
A
–1-dBFSdifferentialanaloginput,andsamplingrate=250MSPS,unlessotherwisenoted.Minimumandmaximumvalues
areacrossthefulltemperaturerangeofT =–40°CtoT =+85°C,AVDD=1.8V,AVDD3V=3.3V,DRVDD=1.8V,
MIN MAX
andIOVDD=1.8V.
2-V FULL-SCALE 2.5-V FULL-SCALE
PP PP
PARAMETER TESTCONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
f =10MHz 73.4 75 dBFS
IN
f =70MHz 73.2 74.7 dBFS
IN
SNR Signal-to-noiseratio
f =170MHz 69.5 72.7 74 dBFS
IN
f =230MHz 72.2 73.4 dBFS
IN
f =10MHz 73.3 74.8 dBFS
IN
f =70MHz 73.1 74.5 dBFS
IN
SINAD Signal-to-noiseanddistortionratio
f =170MHz 68.5 72.7 73.8 dBFS
IN
f =230MHz 71.8 72.6 dBFS
IN
f =10MHz 95 90 dBc
IN
Spurious-freedynamicrange f =70MHz 91 88 dBc
IN
SFDR (includingsecondandthird
harmonicdistortion) fIN=170MHz 79 93 89 dBc
f =230MHz 84 82 dBc
IN
f =10MHz 92 88 dBc
IN
f =70MHz 89 86 dBc
IN
THD Totalharmonicdistortion
f =170MHz 76 90 86 dBc
IN
f =230MHz 82 80 dBc
IN
f =10MHz 95 95 dBc
IN
f =70MHz 91 88 dBc
IN
HD2 2nd-orderharmonicdistortion
f =170MHz 79 93 94 dBc
IN
f =230MHz 84 82 dBc
IN
f =10MHz 95 90 dBc
IN
f =70MHz 96 93 dBc
IN
HD3 3rd-orderharmonicdistortion
f =170MHz 79 94 89 dBc
IN
f =230MHz 86 84 dBc
IN
f =10MHz 102 102 dBc
IN
Worstspur f =70MHz 103 103 dBc
IN
(otherthansecondandthird
harmonics) fIN=170MHz 87 101 95 dBc
f =230MHz 99 93 dBc
IN
f =46MHz,f =50MHz,
1 2 97 95 dBFS
Two-toneintermodulation eachtoneat–7dBFS
IMD
distortion f =185MHz,f =190MHz,
1 2 90 89 dBFS
eachtoneat–7dBFS
20-MHz,full-scalesignalon
channelunderobservation;
Crosstalk 100 100 dB
170-MHz,full-scalesignalon
otherchannel
Recoverytowithin1%(offull-
Clock
Inputoverloadrecovery scale)for6-dBoverloadwithsine- 1 1
cycle
waveinput
Fora50-mV signalonAVDD
PSRR ACpower-supplyrejectionratio PP >40 >40 dB
supply,upto10MHz
ENOB Effectivenumberofbits f =170MHz 11.8 12 LSBs
IN
DNL Differentialnonlinearity f =170MHz ±0.15 ±0.15 LSBs
IN
INL Integratednonlinearity f =170MHz ±0.75 ±3 ±0.9 LSBs
IN
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