Analog Test Signal Generation Using Periodic ΣΔ-Encoded Data Streams

156 Pages·2000·4.07 MB·English

by  Benoit Dufort

ANALOG TEST
SIGNAL GENERATION
USING PERIODIC
~Ll-ENCODED
DATA STREAMS
THE KLUWER INTERNATIONAL SERIES
IN ENGINEERING AND COMPUTER SCIENCE
ANALOG CIRCUITS AND SIGNAL PROCESSING
Consulting Editor: Mohammed Ismail. Ohio State University
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ANALOG TEST
SIGNAL GENERATION
USING PERIODIC
~Ll-ENCODED
DATA STREAMS
by
Benoit Dufort
Philips Research
and
w.
Gordon Roberts
McGill University
~.
"
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
Library of Congress Cataloging-in-Publication Data
A C.I.P. Catalogue record for this book is available
from the Library of Congress.
ISBN 978-1-4613-6968-4 ISBN 978-1-4615-4377-0 (eBook)
DOI 10.1007/978-1-4615-4377-0
Copyright @ 2000 Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers, New York in 2000
Softcover reprint ofthe hardcover lst edition 2000
AH rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted in any form or by any means, mechanical,
photo-copying, recording, or otherwise, without the prior written permis sion
of the publisher, Springer Science+Business Media, LLC
Printed on acid-free pap er.
Table of Contents
Preface ................................................................................................ xi
Chapter 1: Introduction ..................................................................... 1
1.1 Test and Technology Evolution ................................................ 2
1.2 Design-for-Testability (DFT) .................................................... 3
1.3 Motivation for this Book ........................................................... 5
1.4 Outline of Book ......................................................................... 5
Chapter 2: Mixed-Signal Testing ...................................................... 7
2.1 Digital Testing .......................................................................... 8
2.2 Manufacturing Issues ................................................................ 9
2.3 AnaloglMixed-Signal Testing ................................................. 11
2.4 The Changing Requirements of Mixed-Signal Test ............... 14
2.4.1 Evolution with Design and Production Life Cycle ..... 15
2.4.2 Evolution with Circuit Performance ........................... 16
2.5 Built-In Self-Test Schemes ..................................................... 18
2.5.1 CODEC and MODEM Circuits .................................. 18
2.5.2 Transceiver Circuits .................................................... 19
2.5.3 Phase-Lock Loops ....................................................... 21
2.6 Stimulus Generation ................................................................ 21
2.6.1 Direct Digital Frequency Synthesis ............................ 21
vi Table of Contents
2.6.2 l:~ Oscillator ............................................................... 23
2.6.3 Memory-Based l:~ Generators .................................. .24
2.7 Parameter Extraction ............................................................... 25
2.7.1 Code Density Testing .................................................. 25
2.7.2 Correlation Tests ......................................................... 25
2.7.3 On-Chip Digital Sampling Oscilloscope .................... 25
2.8 Summary ................................................................................. 26
Chapter 3: Periodic l:~ Bit Stream Theory .................................... 27
3.1 Periodic Signals and Frequency Domain Description ........... .27
3.1.1 Coherent Signals ......................................................... 31
3.2 l:~ Modulation ........................................................................ 32
3.2.1 Quantization and Performance Metrics ...................... 32
3.2.2 Oversampling Converters ........................................... 34
3.2.3 Noise Shaping ............................................................. 36
3.3 Generating Periodic Bit Streams ............................................ .39
3.3.1 Input Signal ................................................................. 41
3.3.2 Signal and Noise Transfer Function ......................... ..41
3.3.3 Bit Stream Length Selection ..................................... ..41
3.3.4 Sequence Generation ................................................. .42
3.4 Practical Considerations ......................................................... .42
3.4.1 Frequency Resolution ................................................ .42
3.4.2 Amplitude Range and Resolution ............................. ..43
3.4.3 Phase Resolution ....................................................... ..43
3.4.4 Noise Spreading .......................................................... 45
3.4.5 Windowing .................................................................. 50
3.5 Optimization of Periodic Bit Streams ..................................... 50
3.5.1 Varying the Phase ofthe Tone .................................... 51
3.5.2 Varying the Tone Amplitude ...................................... 52
3.6 Performance Comparison of Optimized Bit Streams with Theo-
retical Prediction ..................................................................... 54
3.6.1 SFDR .......................................................................... 54
3.6.2 Signal-to-Noise Ratio .................................................. 55
3.6.3 Power Spectral Density ............................................... 56
3.7 Design Aids ............................................................................. 57
3.7.1 Maximum SFDR ......................................................... 57
3.7.2 Maximum Amplitude .................................................. 59
3.8 Multi-Bit Streams ................................................................... 60
3.8.1 Input Signal ................................................................. 60
Table of Contents vii
3.8.2 Quantizer ..................................................................... 61
3.8.3 Optimization ............................................................... 61
3.9 Alternative Optimizations ....................................................... 61
3.9.1 Optimization with Non-spectral Criteria .................... 61
3.9.2 Periodic :E~ Modulator: Limit Cycles ......................... 63
3.9.3 Genetic Algorithm Optimization ................................ 64
3.10 Summary ............................................................................... 64
Chapter 4: Analog Signal Generation .............................................6 5
4.1 Sinewave Generation .............................................................. 65
4.1.1 Single-Tone ................................................................. 65
4.1.2 Multi-Tone .................................................................. 65
4.2 DC Generation ........................................................................ 66
4.2.1 Pulse Width Modulation (PWM) ................................ 67
4.2.2 Pulse Density Modulation (PDM) or Noise-Shaped DC
Signals ......................................................................... 70
4.2.3 DC Amplitude Resolution .......................................... 73
4.3 Arbitrary Band-Limited Pulse Generation .............................. 73
4.3.1 Triangular Pulses ........................................................ 74
4.3.2 Communication Pulses ............................................... 75
4.3.3 Distorted Pulses .......................................................... 76
4.4 Digital Modulation .................................................................. 78
4.4.1 Amplitude Shift Keying (ASK) .................................. 78
4.4.2 Frequency Shift Keying (FSK) ................................... 81
4.4.3 Phase Shift Keying (PSK) ........................................... 83
4.5 Multi-Bit Generation ............................................................... 84
4.5.1 Dynamic Element Matching ....................................... 84
4.5.2 Periodic Dynamic Element Matching Generation ...... 88
4.6 Implementation Issues ............................................................ 88
4.6.1 Silicon Area ................................................................ 88
4.6.2 One-Bit DAC .............................................................. 90
4.6.3 Analog Filtering .......................................................... 91
4.6.4 No Filtering ................................................................. 91
4.6.5 Filter in the Circuit Under Test ................................... 91
4.6.6 Filter On-Chip ............................................................. 91
4.6.7 Filter Off-chip ............................................................. 92
4.6.8 Clock Jitter .:. ................................................................ 92
4.7 Summary ................................................................................. 95
viii Table of Contents
Chapter 5: Integrated Circuit Prototypes ...................................... 97
5.1 Dual-Tone Multi-Frequency Generator .................................. 97
5.1.1 Frequency Selection .................................................... 97
5.1.2 FPGA Implementation ................................................ 98
5.2 RAM-Based Generator ......................................................... 100
5.2.1 Static RAM ............................................................... 100
5.2.2 Address Generator .................................................... 100
5.2.3 Silicon Implementation ............................................. 101
5.2.4 RAM Generator Measured Results ........................... 102
5.3 Shift-Register Based Generator ............................................ 10 4
5.3.1 Custom Dual-Phase Flip-flop ................................... 105
5.3.2 Variable Aspect Ratio ............................................... 106
5.3.3 Silicon Implementation and Results ......................... 106
5.3.4 Comparison with RAM-Based Generator ................. 107
5.4 High-Speed CMOS Generator .............................................. 108
5.4.1 Generator Design ...................................................... 10 8
5.4.2 High-speed Clocking: CMOS Phase Locked Loop .. 110
5.4.3 Bitstream Filtering .................................................... 110
5.4.4 Silicon Implementation ............................................. 111
5.4.5 Results ....................................................................... 111
5.5 Summary ............................................................................... 113
Chapter 6: Application to Arbitrary Waveform Generators ..... 115
6.1 Periodic L~ Multi-Bit Streams ............................................. 116
6.2 Increasing the Performance of A WGs .................................. 117
6.2.1 In-Band Tone Test .................................................... 118
6.2.2 Out-Of-Band Tone Test ............................................ 119
6.2.3 Trade-off Between Resolution and Bandwidth ......... 121
6.3 Non-Ideal Behavior ............................................................... 122
6.3.1 Clock Jitter ................................................................ 122
6.3.2 DAC Static Non-linearities ....................................... 122
6.3.3 Dynamic Non-linearities ........................................... 122
6.4 Calibration ............................................................................. 123
6.4.1 Clock Jitter ................................................................ 123
6.4.2 Static Calibration ...................................................... 124
6.4.3 Pseudo-Dynamic Calibration .................................... 127
6.4.4 Dynamic Calibration ................................................. 128
6.5 Future Arbitrary Waveform Generator ................................. 131
Table of Contents ix
6.6 Summary ............................................................................... 133
Chapter 7: Conclusions .................................................................. 135
7.1 Summary ............................................................................... 135
7.2 The Periodic Bitstream Approach ......................................... 135
7.3 On-Chip Generator for Analog and Mixed-Signal BIST ...... 136
7.4 Application to Arbitrary Waveform Generators ................... 137
7.5 Future Work .......................................................................... 137
References ........................................................................................ 139
Index ................................................................................................. 147
Preface
The trend in the microelectronic field has been for denser and faster
integrated circuits. Today we can integrate over 20 million transistors on a single chip,
and this number is expected to double in the next year and a half. Until recently, most
electronic systems consisted of one or many printed circuit boards, containing
multiple integrated circuits (lCs) each. Recent advances in IC design methods and
manufacturing technologies enable complete systems to be integrated on a single Ie.
These so-called system chips offer advantages such as higher performance, lower
power consumption, and smaller volume and weight, when compared to their
traditional multi-chip equivalents. System chips typically contain mixed technologies,
such as logic, memories of various types, and numerous analog building blocks.
Many system chips are designed by embedding large reusable building blocks,
commonly called cores. Design reuse offers to speed up the design and enables design
expertise to be imported from third party vendors.
Besides the obvious need for standards to guide their integration, the need
for individual verification of each core is paramount for this approach to succeed, as
the IC design community is now divided into core users and core providers. In
traditional System-on-Board (SOB) design, the components that go from provider to
the user are packaged ICs, which are designed, manufactured, and tested as stand
alone components. The user of these components is then only concerned with
manufacturing defects that appear in the component interconnections. In System-on
Chip (SOC) design, the components are untested cores, where detailed knowledge of
the design is not readily available. Hence, the core user becomes responsible for
manufacturing and testing the entire system chip with little to go on. Rather, it
appears as though the industry will move towards a position where the core provider
will be expected to supply the test solution for its own core and pass on all test details