Analog Circuit Testing - Department of Electrical Engineering and

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Analog Circuit Testing
(cid:127) Test Problems
(cid:127) Basic Components / Parameters
(cid:127) Test Methods
−
DSP Based
−
Design for Test
−
Built-in Self-Test
−
Algorithmic Method
Mixed/analog-signal testing.1
Test Problems
(cid:127) Continuous signals in analog circuits
(cid:127) Fault models
(cid:127) Device parameters
(cid:127) Test time
(cid:127) Test effectiveness (fault coverage)
(cid:127) Test cost
Mixed/analog-signal testing.2
Typical Analog Components
(cid:127) Operational amplifiers
(cid:127) Integrators
(cid:127) DAC & ADC
(cid:127) Phase lock loops
(cid:127) Filters
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Operational Amplifiers
Property
Ideal op-amp
1.voltage-controlled voltage source
(cid:1)
2.infinite voltage gain
(cid:1) 3.infinite input impedance
4.zero output impedance
5.infinite bandwidth
V
a
i =0
a (cid:1) 6.no offset voltage
A(V -V )
(cid:2)
V a b
b
7.infinite CMRR
i =0
b
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Property of real op-amp
≅≅≅≅
1.finite gain(practical op-amps A 102~ 104)
2.finite linear range(V >V >GND)
DD o
3.offset voltage
−
input offset voltage V is defined as the differential
offset
input voltage needed to restore V =0
o
−
for MOS op-amps, V is about 5~15mv
offset
for BJT op-amps, V is about 1~2mv
offset
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Property of real op-amp(con’t)
4.Common Mode Rejection Ration(CMRR)
−
The CMRR measure how much the op-amp can suppress
common-mode signals at its input
(cid:6)(cid:2)(cid:7) (cid:5)+ (cid:2)(cid:3)(cid:4)
−
Common-mode input voltage V =
(cid:1)
in.c
Differential-mode input voltage V =V -V
in,d a b
Differential gain A = V / V
d o in,d
Common-mode gain A = V / V
c o in,c
CMRR= (A /A ) or 20 log (A /A ) in dB (Typically 60~80dB)
d c 10 d c
(cid:1)
(cid:1)
V
(cid:1)
a (cid:1)
(cid:1) +
V +
V (cid:2) V
b
in.c o V
- o
-
Common-mode input
Differential-mode input
Mixed/analog-signal testing.6
Property of real op-amp(con’t)
5.Frequency Response
−
Limited bandwidth(typically, 100MHz unity-gain
bandwidth)
−
Gain decreases at high frequencies , because
a.stray capacitances
b.finite carrier mobilities
µµµµ
6.Slew Rate(typically,for MOS op-amps,1~50V/ s)
−
The maximum rate of output change dV /dt
o
7.Nonzero Output Resistance
− Ω
Typically,0.1~5k
−
Large Ro will limit frequency response when a
capacitor is connected to its output
Mixed/analog-signal testing.7
Characteristics of Op-Amps
property ideal Practical(typical)
Open-loop gain Infinite Very high(A=102~104)
Open-loop bandwidth Infinite Dominant pole (
100MHz unity-gain
bandwidth)
Common-mode rejection Infinite High(60~80dB)
ratio Ω
Infinite High(>100M )
Input resistance Ω
Zero Low(0.1~5k )
Output resistance µ
Zero Low(<0.5 A)
Input current
Zero Low(<10mV,<0.2nA)
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Operational-amplifier architectures
The two-stage architecture
V
Level shifting
a Output
Differential input
Buffer V
Differential–to-single-ended
amplifier o
V stage
b Gain stage
Differential amp provides:
−
high input impedance
−
large CMRR
−
low offset voltage
−
high gain
Mixed/analog-signal testing.9
Operational-amplifier architectures(con’t)
Second block provides:
−
level shift
−
added gain
−
differential-to-single-ended conversion
Output stage provides:
−
low output impedance
−
large driving capability
Mixed/analog-signal testing.10