An Ultra Low Power ADC for Wireless

147 Pages·2014·6.94 MB·English

An Ultra Low Power ADC for Wireless
Micro-Sensor Applications
by
Naveen Verma
B.A.Sc., Electrical Engineering and Computer Engineering, University
of British Columbia
Submitted to the Department of Electrical Engineering and Computer
Science
in partial fulfillment of the requirements for the degree of
Master of Science in Electrical Engineering and Computer Scienco
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
June 2005
© 2005 Massachusetts Institute of Technology. All rights reserved.
A uthor .......................... ......
Department of Electrical Engineering and Computer Science
May 16, 2005
C ertified by .................... ................ .....................
Anantha P. Chandrakasan
Professor of Electrical Engineering
Thesis Supervisor
Accepted by..... ..........
Arthur C. Smith
Chairman, Departmental Committee on Graduate Students
MASSACHUSETTS
INS E
OF TECHNOOGY
BARKER
MAR 0 3 2006
LIBRARIES
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An Ultra Low Power ADC for Wireless Micro-Sensor
Applications
by
Naveen Verma
Submitted to the Department of Electrical Engineering and Computer Science
on May 16, 2005, in partial fulfillment of the
requirements for the degree of
Master of Science in Electrical Engineering and Computer Science
Abstract
Autonomous micro-sensor nodes rely on low-power circuits to enable energy har-
vesting as a means of sustaining long-term, maintenance free operation. This work
pursues the design of an ultra low-power analog-to-digital converter (ADC) whose
sampling rate and resolution can be scaled to dynamically recover power savings.
The proposed ADC has a sampling rate of 0-100 kS/s and a resolution of either
12 or 8 bits. The design is based on the successive approximation register architec-
ture (SAR), which is suitable for scaleable, micro-power operation. Specifically, the
number of active blocks has been minimized to allow efficient power-gating, which, in-
turn, has been leveraged to implement scalability features. Several new techniques to
improve the efficiency of the ADC have been developed and employed. Analog offset
calibration in the regenerative latch is used, to improve the power-delay product of
the comparator; pre-amplifier cascade optimization is performed with consideration to
thermal noise limitations; weak-inversion biasing is employed in the active amplifiers;
passive switch-capacitors are used to generate the auto-zero reference voltage such
the CMRR of the ADC is maximized; integrated capacitors are laid-out in a new
common-centroid arrangement that minimizes edge effects; finally, the sub-DAC's
transmission gain is adjusted to reduce non-linearities caused by the attenuating ef-
fects of parasitics.
The ADC has been fabricated in a 0.18pLm CMOS technology. All circuits are
powered using a IV supply, though bootstrapping is used internally. At a resolution
of 12-bits, and a sampling rate of 100 kS/s, the power consumption of the entire
ADC core is 26pW. The SNDR of the converter with a 48 kHz input tone is 65dB
(10.55 ENOB) and the SFDR is 71dB. The power consumption decreases linearly
with sampling rate, and is measured to be approximately 200nW at 500 S/s.
Thesis Supervisor: Anantha P. Chandrakasan
Title: Professor of Electrical Engineering
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Acknowledgements
This thesis has been a major accomplishment. It is not, however, my accomplishment
alone. The immense support and friendship I've received from so many over the course
of my degree and education so far, is perhaps the aspect most worth remembering.
Let me start by thanking them here.
Firstly, I must express my gratitude to my advisor and role model, Professor
Anantha Chandrakasan. Anantha forces me to do my best; how is it that I can spend
months analyzing a problem, and the first time I present it to him, I get a question
I hadn't even thought of? But, most importantly, I thank Anantha for giving me
something to strive towards.
Of course, non-technically, the biggest impact in my life is courtesy of my mom and
dad. Saying thank you to you guys is too trivial and inconsequential for everything
you have done and meant. I only hope that you know, as you always do, how much
your support means to me on a daily basis.
My sisters, Angelee and Serena, have played a very important role, not only in
my life, but specifically in the completion of this thesis. Thank you, both, for making
it such a high priority to keep in tact my ability to write prose. Of course, your
encouragement has meant even more.
Engineering education, a microcosm of life, is an arduous process. I've gotten
support, all the way, from my good friend, Sean. Neither of us quite fits into the EE
scene, but we get each other through it, and, at the end of it, we have a good laugh.
There is a group of masters who took it personally to make sure I understood
what engineering really is: a tall order, considering, at the time, I barely understood
V=IR. Thank you Dr. Lawrence, Dr. Jaeger, Dr. Pulfrey, and Dr. Salcudean.
Here at MIT, I wish to thank everyone from Ananthagroup. I'm lucky to be
associated with such a bright group, that continually inspires me to be more creative.
Finally, I would like to acknowledge National Semiconductor for providing fabri-
cation services for the prototype chip, as well as their development help and CAD
support.
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Contents
1 Introduction 19
1.1 Requirement Specifications . . . . . . . . . . . . . . . . . . . . . . . . 20
1.1.1 Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.1.2 Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.1.3 Scalability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.1.4 Input Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.2 Architecture Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2 Precision Limitations 25
2.1 Low Overdrive of MOS Switches . . . . . . . . . . . . . . . . . . . . . 25
2.2 Charge Injection Errors . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3 Mismatch of Passive Elements . . . . . . . . . . . . . . . . . . . . . . 27
2.4 Mismatch of Active Elements . . . . . . . . . . . . . . . . . . . . . . 27
2.5 Device Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.6 Threshold Voltage Hysteresis . . . . . . . . . . . . . . . . . . . . . . . 30
2.7 Other Error Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3 Successive Approximation Conversion 33
3.1 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2 Differential Successive Approximation ADC . . . . . . . . . . . . . . 35
3.3 Analysis of Error Sources . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.3.1 Capacitor Mismatch . . . . . . . . . . . . . . . . . . . . . . . 39
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3.3.2 DAC Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3.3 Reference Voltage Error . . . . . . . . . . . . . . . . . . . . . 41
3.3.4 Comparator Offset . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3.5 Sampling Switch Non-Linearity . . . . . . . . . . . . . . . . . 42
3.3.6 Comparator Thermal Noise . . . . . . . . . . . . . . . . . . . 42
3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4 Architecture Design and Theory 45
4.1 Global Architecture and Concepts . . . . . . . . . . . . . . . . . . . . 45
4.1.1 Conversion Plan . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.1.2 Sample Rate Scaling . . . . . . . . . . . . . . . . . . . . . . . 47
4.1.3 Resolution Modes . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.1.4 Self-Timed Bit Cycling . . . . . . . . . . . . . . . . . . . . . . 51
4.2 Block Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.2.1 Comparator Architecture . . . . . . . . . . . . . . . . . . . . . 54
4.2.2 DAC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.2.3 SAR Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5 Circuit Design 75
5.1 DAC Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.1.1 Switch Network . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.1.2 Capacitor array . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.2 Comparator Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . 91
5.2.1 Preamplifers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.2.2 Offset-Calibrating Latch . . . . . . . . . . . . . . . . . . . . . 96
5.2.3 Latch Level Restorer . . . . . . . . . . . . . . . . . . . . . . . 106
5.3 SAR Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.4 Clock Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.5 Charge Pump and Voltage Multiplier . . . . . . . . . . . . . . . . . . 112
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6 Testing and Characterization 115
6.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.2 Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.2.1 Static Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.2.2 Dynamic Noise and Linearity . . . . . . . . . . . . . . . . . . 120
6.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.4 Comparision Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
7 Discussions and Future Work 129
7.1 Effects of Applied optimizations . . . . . . . . . . . . . . . . . . . . . 130
7.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.2.1 Digital Optimization . . . . . . . . . . . . . . . . . . . . . . . 132
7.2.2 Programmable On-Chip Post-Filtering . . . . . . . . . . . . . 132
7.2.3 Resolution Scalable DAC . . . . . . . . . . . . . . . . . . . . . 132
7.2.4 Active Input Switch . . . . . . . . . . . . . . . . . . . . . . . 132
A ADC Fundamentals 135
A.1 Linear Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . 135
A.1.1 Ideal ADC Model . . . . . . . . . . . . . . . . . . . . . . . . . 136
A.1.2 Quantization Noise . . . . . . . . . . . . . . . . . . . . . . . . 136
A.2 Non-Ideal ADC Model . . . . . . . . . . . . . . . . . . . . . . . . . . 137
A.2.1 Effective Resolution . . . . . . . . . . . . . . . . . . . . . . . . 138
A.2.2 Random Noise in SAR ADCs . . . . . . . . . . . . . . . . . . 138
A.3 Performance Normalization . . . . . . . . . . . . . . . . . . . . . . . 139
A.3.1 Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 139
A.3.2 Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
A.3.3 Figure of Merit . . . . . . . . . . . . . . . . . . . . . . . . . . 141
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