An on-chip input driver for a high-voltage SAR ADC

49 Pages·2014·3.8 MB·English

An On-Chip Input Driver for a High-Voltage SAR
ADC
by
Kevin Robert Linke
Submitted to the Department of Electrical Engineering and Computer
Science
in partial fulfillment of the requirements for the degree of
Master of Science in Electrical Engineering and Computer Science
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY JUL 15 2014
June 2014
LIBRARIES
@ Massachusetts Institute of Technology 2014. All rights reserved.
Signature redacted
Author .................
Department of Electrical Engineering and Computer Science
May 9, 2014
Signature redacted
Certified by.
Micah G. O'Halloran
Design Engineering Section Lead, Linear Technology
Thesis Supervisor
redacted . .
Certified by... .Signature
Charles G. Sodini
LeBel Professor, Electrical Engineering
Signatu re redacted Thesis Supervisor
A ccepted by ..... ........... .......................................
Prof. Albert R. Meyer
Chairman, Masters of Engineering Thesis Committee
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An On-Chip Input Driver for a High-Voltage SAR ADC
by
Kevin Robert Linke
Submitted to the Department of Electrical Engineering and Computer Science
on May 9, 2014, in partial fulfillment of the
requirements for the degree of
Master of Science in Electrical Engineering and Computer Science
Abstract
This thesis describes the design of a novel on-chip input driver for a SAR ADC. The
driver achieves performance gains relative to off-chip alternatives by being integrated
into the signal path of the ADC between the sampling switches and sampling ca-
pacitor. This placement allows for auto-zeroing the offset of the driver and reducing
flicker noise. Additional performance benefits are possible because the driver can be
optimized for the specific load and timings of the ADC. The most important ben-
efit of an on-chip input driver is that it simplifies the design process for the ADC
user by eliminating the external op-amp and reducing the constraints on the external
filter by reducing input current load. Design simplicity is especially important to
users in high-voltage SAR ADC applications, so the input driver is designed for an
ADC with a 10.24 V input range and 15 V supply rails. This high-voltage input
relaxes noise and headroom constraints, but makes device overvoltage a significant
concern. The driver is designed in a BiCMOS process, and simulation results with a
computer-modeled ADC are presented here. In these simulations, the driver achieves
a THD of -124.7 dB at 2 kHz and a noise voltage spectral density of 5.5 nV/v Hz
with a power consumption of 27.6 mW. The LT1469, an example of a state-of-the-art
external input driver, has a THD of -123 dB at 2 kHz, a noise voltage spectral density
of 5 nV/VHz, and a power consumption of 123 mW.
Thesis Supervisor: Micah G. O'Halloran
Title: Design Engineering Section Lead, Linear Technology
Thesis Supervisor: Charles G. Sodini
Title: LeBel Professor, Electrical Engineering
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Acknowledgments
First and foremost, I would like to thank Micah O'Halloran, my thesis supervisor at
Linear Technology. Micah was an outstanding supervisor who always found time to
answer my questions and offer advice. He is responsible for much of my understanding
of analog circuit design. Without his assistance and expertise, this project would not
have been possible. I would also like to thank two other Linear engineers, Andrew
Thomas and Joe Sousa. Both were excellent sources of help and advice. Andrew in
particular always had insightful answers to my toughest questions.
I am thankful to Prof. Charles Sodini, my faculty thesis advisor, for his help during
the project, as well as his review of the thesis and suggestions for improvement. I am
also appreciative of Prof. Sodini's advising throughout my MIT experience.
Finally, I would like to thank my parents, Kathy and Bob, for their love, support,
and guidance. Without their parenting effort I would not be where I am or who I am
today.
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Contents
1 Introduction 13
1.1 Background . . . . . . . . . . . . . 13
1.2 Project Motivation . . . . . . . . . 16
1.3 Approach ................. 18
1.4 Thesis Organization . . . . . . . . . 21
2 Input Driver Circuit Design 23
2.1 Performance Goals . . . . . . . . . 23
2.2 Driver Circuit Design Summary . . 26
2.3 Low-Voltage Driver Core . . . . . . 28
2.4 Low-Voltage Rail Generator Circuit 32
2.5 Protection Devices . . . . . . . . . 35
2.6 Sample Switch. . . . . . . . . . . . 37
3 Simulation 39
3.1 ADC Test Bench . . . . . . . . . . . 39
3.2 Total Harmonic Distortion . . . . . . 40
3.3 Output Noise . . . . . . . . . . . . . 41
3.4 Power Consumption . . . . . . . . . 43
3.5 Gain Error and Integral Nonlinearity 43
3.6 Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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4 Conclusion 47
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List of Figures
1-1 Simplified schematic of SAR ADC . . . . . . . . . . . . . . . . 14
1-2 Equivalent circuit for the analog input of a typical SAR ADC 15
1-3 LTC2389 recommended external input driver . . . . . . . . . . 16
1-4 Simplified schematic of SAR ADC with input drivers..... 19
1-5 Input driver system diagram . . . . . . . . . . . . . . . . . . . 22
2-1 Full driver schematic . . . . . . . . . . . . 27
2-2 Low-voltage driver core schematic . . . . . 30
2-3 Driver core mirror schematic . . . . . . . . 31
2-4 Low-voltage rail generator schematic . . . 34
2-5 Protection clamps . . . . . . . . . . . . . . 36
2-6 Simplified model of ADC sampling switch 38
3-1 Diagram of simulated ADC . . . . . . . . . . . . . . . . . . . . . . . 4 0
3-2 DFT of ADC with input driver . . . . . . . . . . . . . . . . . . . . . 4 1
3-3 Input driver noise voltage spectral density . . . . . . . . . . . . . . . 4 2
3-4 Gain error and INL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4
3-5 Overvoltage testing waveforms . . . . . . . . . . . . . . . . . . . . . . 4 5
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