an integrated, lossless, and accurate current-sensing technique for high-performance switching ...

290 Pages·2006·3.47 MB·English

by  Pooya Forghani

AN INTEGRATED, LOSSLESS, AND ACCURATE
CURRENT-SENSING TECHNIQUE FOR
HIGH-PERFORMANCE SWITCHING REGULATORS

A Dissertation
Presented to
The Academic Faculty

by

H. Pooya Forghani-zadeh

In Partial Fulfillment
of the Requirements for the Degree
Doctor of Philosophy in the
School of Electrical and Computer Engineering

Georgia Institute of Technology
August 2006

Copyright 2006 by H. Pooya Forghani-zadeh
AN INTEGRATED, LOSSLESS, AND ACCURATE
CURRENT-SENSING TECHNIQUE FOR
HIGH-PERFORMANCE SWITCHING REGULATORS

Approved by:

Dr. G. Rincón-Mora, Advisor Dr. T. Habetler
School of Electrical and School of Electrical and
Computer Engineering Computer Engineering
Georgia Institute of Technology Georgia Institute of Technology

Dr. M. Leach Dr. E. Harrell
School of Electrical and School of Mathematics
Computer Engineering Georgia Institute of Technology
Georgia Institute of Technology

Dr. D. Divan
School of Electrical and
Computer Engineering
Georgia Institute of Technology

Date Approved:
June 1, 2006
ACKNOWLEDGEMENTS
Completing a Ph.D. thesis requires use of someone’s accumulated knowledge
from childhood to graduate school. Therefore, I would like to thank all of my teachers,
instructors, and professors through the last twenty years of my life in school.
In particular, my deepest appreciation goes to my advisor, Prof. Gabriel Rincón-
Mora, for his invaluable advice on professionalism, problem solving, and research.
Insightful discussions with my fellow colleagues Min Chen, Huseyin Dinc, Vishal Gupta,
Neeraj Keskar, Ajay Kumar, Luke Milner, and Erick Torres at Georgia Institute of
Technology Analog and Power IC design laboratory have improved the quality of my
work, and I extend my appreciation to them. Technical and financial support of Intersil
Corporation and services of MOSIS organization in fabricating the test chips have been a
great asset in my program and are appreciated. Additionally, I would like to thank Intersil
portable power management design group members and in particular Mr. John Seitters as
well as Mr. Todd Harrison from Texas Instruments for their inspiration, comments, and
recommendations during design reviews. Last but not least, I would like to thank my
parents and sister for their support and encouragement.

iii
TABLE OF CONTENTS
Page
ACKNOWLEDGEMENTS............................................................................................iii
LIST OF TABLES.........................................................................................................ix
LIST OF FIGURES........................................................................................................xi
LIST OF SYMBOLS AND ABBREVIATIONS...........................................................xx
SUMMARY.................................................................................................................xxi
CHAPTER 1: INTRODUCTION....................................................................................1
1.1. Current Sensing in Switching Regulators......................................................2
1.2. Research Objective .......................................................................................4
1.3. Market Demand............................................................................................9
CHAPTER 2: STATE-of-THE-ART CURRENT-SENSING TECHNIQUES................12
2.1. Current-Sensing Applications in Switching Regulators ...............................12
2.1.1. Protection.........................................................................................12
2.1.2. Frequency Compensation.................................................................13
2.1.3. Droop Compensation........................................................................13
2.1.4. Mode Hop........................................................................................14
2.1.5. Inductor Multipliers..........................................................................15
2.1.6. Single-Inductor Multiple-Output Converters.....................................15
2.1.7. Current-Sharing Techniques.............................................................16
2.2. Current-Sensing Techniques for Switching Regulators................................16
2.2.1. Sense Resistors.................................................................................19
2.2.2. MOSFET-RDS.................................................................................21
2.2.3. Sense-FET Technique.......................................................................23
2.2.4. Hall-Effect Sensors...........................................................................24
2.2.5. Transformer Technique ....................................................................25
2.2.6. Observer Approach...........................................................................25
2.2.7. I-Average Technique........................................................................26
2.2.8. Matching Complimentary Filter........................................................26
iv
2.3. Problems of State-of-the-Art Techniques and Motivations for This Research
..........................................................................................................................27
Summary.......................................................................................................................30
CHAPTER 3: SELF-CALIBRATING, LOSSLESS, AND, ACCURATE CURRENT-
SENSING CIRCUIT.....................................................................................................31
3.1. Proposed Approach.....................................................................................31
3.2. Discrete Verification...................................................................................38
3.2.1. Current-Sensing Filter......................................................................39
3.2.2. Start-Up Hardware Implementation..................................................40
3.2.3. Experimental Results........................................................................44
3.3. Integrated Circuit Challenges......................................................................46
Summary.......................................................................................................................53
CHAPTER 4: ACCURACY..........................................................................................54
4.1. Inductor Model...........................................................................................54
4.2. Errors..........................................................................................................59
4.2.1. Operating-Point Errors...................................................................61
4.2.2. Random Offsets.............................................................................62
4.2.3. Systematic Offsets.........................................................................62
4.2.4. Tuning-Loop Errors.......................................................................64
4.2.5. Calibration-Loop Errors.................................................................65
4.3. Specification Requirements.........................................................................67
Summary.......................................................................................................................68
CHAPTER 5: CURRENT-MODE CONTROLERS.......................................................72
5.1. Types of Switching Regulators....................................................................72
5.2. Controller Schemes.....................................................................................75
5.3. Current-Mode Controller.............................................................................78
5.3.1. Operation.........................................................................................79
5.3.2. Compensation...................................................................................80
5.3.3. Sub-harmonic Oscillation.................................................................93
5.3.4. Transient Response...........................................................................96
5.4. Controller Design......................................................................................100
v
CHAPTER 6: CIRCUIT DESIGN...............................................................................104
6.1. System......................................................................................................104
6.1.1. Hierarchy.......................................................................................105
6.1.2. Floorplanning.................................................................................107
6.1.3. Design Flow...................................................................................108
6.2. Circuit Blocks...........................................................................................109
6.2.1. G -C Filter.....................................................................................109
m
6.2.2. Tuning............................................................................................130
6.2.3. Calibration.....................................................................................137
6.2.4. Tuning/Calibration/G -C Filter Clock Generator............................148
m
6.2.5. Current-Sensing Output Inverter.....................................................149
6.2.6. Test-Current Generator...................................................................150
6.2.7. Wave Generator..............................................................................153
6.2.8. Current-Mode Controller................................................................161
6.2.9. Error Amplifier...............................................................................164
6.2.10. Summing Comparator...................................................................166
6.2.11. Driver and Dead-Time Controller (DTC)......................................167
6.2.12. Digital Core..................................................................................172
6.2.13. Voltage Reference Network and Bias Generator...........................175
6.2.14. Temperature Compensation Circuits.............................................177
6.3. Final Chip.................................................................................................178
6.3.1. Design Cycles.................................................................................178
6.3.2. Final Chip Top Level......................................................................179
6.3.3. Top-Level Simulation Plan.............................................................184
6.3.4. Layout............................................................................................185
Summary.....................................................................................................................188
CHAPTER 7: SYSTEM EXPERIMENTAL EVALUATION......................................189
7.1. Test Bed....................................................................................................189
7.1. Test Instruments........................................................................................191
7.2. System-Level Experimental Results..........................................................191
7.4. Issues and Fixes........................................................................................204
vi
Summary.....................................................................................................................208
CHAPTER 8: CONCLUSIONS..................................................................................209
8.1. Contributions............................................................................................209
8.2. Comparison to State-of-the Art..................................................................215
8.2.1. Advantages.....................................................................................215
8.2.2. Drawbacks......................................................................................216
8.3. Recommendations.....................................................................................217
8.4. The Future.................................................................................................218
APPENDIX A: A FAST AND RELIABLE TOP-LEVEL SIMULATION STRATEGY
FOR MIXED-SIGNAL ICs AND ITS APPLICATION TO DC-DC CONVERTERS..221
A.1. Switching DC-DC Converters..................................................................222
A.1.1. Operation.......................................................................................222
A.1.1. Macro Models ...............................................................................224
A.2. Top-Level Verification Flow....................................................................224
A.2.1. Design Flow..................................................................................224
A.2.2. Proposed Top-Level Simulation Plan.............................................225
A.2.3. Determining the Optimal Replacement Order from a Set of Screening
Simulations..............................................................................................228
A.3. Numerical Case Study Results..................................................................230
APPENDIX B: PCB LAYOUT TECHNIQUES FOR SWITCHING POWER SUPPLY
CIRCUITS..................................................................................................................237
B.1. Modeling Connections..............................................................................238
B.2. PCB Layout Guidelines............................................................................243
B.2.1. Functionality..................................................................................243
B.2.2. Accuracy.......................................................................................244
B.2.3. Noise.............................................................................................246
B.2.4. Radiated Electro-Magnetic Interference (EMI)..............................247
B.3. Measurements..........................................................................................249
B.3.1. Test Points.....................................................................................249
B.3.2. Ground Loops................................................................................249
Summary.....................................................................................................................251
vii
REFERENCES............................................................................................................253
VITA...........................................................................................................................268
viii
LIST OF TABLES
Page
Table 1.1— Summary of state-of-the-art lossless current-sensing techniques...................4
Table 1.2—Proposed current-sensing module specifications............................................9
Table 1.3—Test switching regulator specifications..........................................................9
Table 2.1—Current sensing and control schemes for switching regulators.....................13
Table 2.2—Comparison of the properties of state-of-the-art current-sensing techniques.29
Table 2.3—Comparison between state-of-the-art current-sensing techniques.................30
Table 3.1—Proposed current-sensing module specifications..........................................52
Table 3.2— Switching regulator specifications..............................................................53
Table 4.1—Effects of temperature, operating current, and operating frequency on current-
sensing circuit..............................................................................................62
Table 4.2—Specification of blocks derived from error budget.......................................69
Table 4.3—Accuracy of the proposed self-calibrating technique versus basic filter
scheme.........................................................................................................70
Table 5.1—Relationships of key voltages and currents in switching regulators..............75
Table 5.2—Summary of control techniques for switching regulators.............................78
Table 5.3—Specifications for a buck converter used in a Li-Ion battery-supplied
handheld micro-processor application........................................................101
Table 5.4 List of design parameters to satisfy specification of Table 5.3......................103
Table 6.1— Hierarchy of the final chip........................................................................106
Table 6.2— Summary of dynamic offset cancellation techniques................................112
Table 6.3— Summary of continuous-time auto-zeroing techniques..............................113
Table 6.4— G -C filter key design parameters............................................................123
m
Table 6.5— Specification compliance matrix of g -C filter.........................................130
m
Table 6.6— Specification compliance matrix tuning loop............................................137
Table 6.7— Specification compliance matrix for calibration loop................................147
Table 6.8— Current generator specification compliance matrix...................................153
Table 6.9— Comparison of the proposed and conventional schemes...........................158
ix
Table 6.10— Wave generator specification compliance matrix....................................160
Table 6.11— Error-amplifier specifications compliance matrix...................................165
Table 6.12— Summing-comparator specification compliance matrix..........................167
Table 6.13— Specification compliance matrix of driver and dead-time controller (DTC).
..................................................................................................................170
Table 6.14— Description of the transient events at start-up.........................................173
Table 6.15— Specification compliance matrix of voltage reference and bias network.176
Table 6.16— Summary of design cycles......................................................................179
Table 6.17— Final-chip pin description.......................................................................183
μ
Table 6.18— Layout area of the key blocks of the propose IC in AMI’s 0.5 m process.
..................................................................................................................186
Table 7.1—Self-learning current-sensing circuit specifications based on experimental
results........................................................................................................200
Table 7.2—Current-mode controller specifications based on experimental results.......203
Table 7.3—Table of final chip issues and their proposed fixes.....................................208
Table 8.1—Summary of contributions.........................................................................213
Table 8.2—List of published and submitted papers......................................................214
Table 8.3—Comparison of the proposed system with the state of the art current-sensing
techniques..................................................................................................217
Table A.1— Case study results of the top-level replacement sequence. .......................232
Table B.1—Summary of circuit-driven PCB design approach.....................................252

x