an accurate, trimless, high psrr, low-voltage, cmos - CiteSeer

157 Pages·2007·2.42 MB·English

by  Vishal Gupta

AN ACCURATE, TRIMLESS, HIGH PSRR, LOW-VOLTAGE,
CMOS BANDGAP REFERENCE IC

A Dissertation
Presented to
The Academic Faculty

by

Vishal Gupta

In Partial Fulfillment
of the Requirements for the Degree
Doctor of Philosophy in the
School of School of Electrical and Computer Engineering

Georgia Institute of Technology
August 2007

COPYRIGHT 2007 BY VISHAL GUPTA
AN ACCURATE, TRIMLESS, HIGH PSRR, LOW-VOLTAGE,
CMOS BANDGAP REFERENCE IC

Approved by:

Dr. Gabriel A. Rincón-Mora, Advisor Dr. Pamela Bhatti
School of Electrical and Computer School of Electrical and Computer
Engineering Engineering
Georgia Institute of Technology Georgia Institute of Technology

Dr. W Marshall Leach Jr. Dr. Thomas Morley
School of Electrical and Computer School of Mathematics
Engineering Georgia Institute of Technology
Georgia Institute of Technology

Dr. Farrokh Ayazi
School of Electrical and Computer
Engineering
Georgia Institute of Technology

Date Approved: July 03, 2007
To my Mother, my clearest vision of God
ACKNOWLEDGEMENTS

I would like to thank God for granting me the perseverance and opportunities to
pursue my goals and dreams.
I wish to thank my family – my parents, Inderpal and Shardarani Gupta, for their
unconditional love, my brother, Vikas Gupta, for this constant, fatherly encouragement,
my sister, Sujata Mittal, for her doting affection, and my loving wife, Tarang Taunk,
whose unwavering support has been the cornerstone of my achievement. Without their
love, this dissertation would not have seen the light of day.
I express my deepest gratitude to my advisor, Dr. Gabriel A. Rincón-Mora, whose
sound technical input, sage advice, and immaculate professionalism have left an indelible
impression on my technical skills and professional ethics.
The financial support of Texas Instruments, Inc. was invaluable and I would like
to express my sincere thanks. In particular, I would like to express my appreciation for
the valuable technical feedback provided by my mentors Dr. Ramanathan Ramani and
Dr. Prasun Raha.
Technical discussions with my colleagues at the Georgia Tech Analog and Power
IC Lab were an integral part of my research and I grateful to them for these exchanges. I
would also like to thank Dr. Rincón-Mora’s administrative assistant, Marge Boehme, for
assisting and supporting my research activities.
Finally, I would like to thank all my friends for providing me with spiritual
nourishment throughout my program.

iv
TABLE OF CONTENTS
Page
ACKNOWLEDGEMENTS iv
LIST OF TABLES viii
LIST OF FIGURES ix
LIST OF SYMBOLS AND ABBREVIATIONS xiii
SUMMARY xiv
CHAPTER
1 INTRODUCTION 1
1.1 The Basic Bandgap Reference 1
1.2 Primary Specifications 4
1.3 Impact of the System-on-Chip (SoC) Paradigm 7
1.4 Research Objectives 9
1.5 Synopsis 12
2 ERROR SOURCES 14
2.1 Process Variations and Mismatch 14
2.2 Package Shift 22
2.3 Power-Supply Variations 24
2.4 Load Variations 29
2.5 Temperature Variations 31
2.6 Summary of Error Sources 32
2.7 Synopsis 33
3 TRIMLESS ACCURACY 34
3.1 Trimming 34
v
3.2 Switching Solutions 36
3.3 Self-Calibration Schemes 39
3.4 Survivor Strategy 41
3.5 Synopsis 58
4 HIGH PSRR 60
4.1 State-of-the-Art Techniques 60
4.2 Proposed Strategy 63
4.3 Synopsis 70
5 LOW OUTPUT IMPEDANCE 71
5.1 Challenges in an SoC Environment 71
5.2 Proposed CMOS Bandgap Reference 73
5.3 Synopsis 85
6 SYSTEM DESIGN 86
6.1 Review of Proposed Techniques 86
6.2 System-Level Issues 90
6.3 Measurement Results 94
6.4 Discussion: Impact of the Survivor Strategy 101
6.5 Synopsis 103
7 CONCLUSIONS 105
7.1 Challenges 105
7.2 Enabling Techniques 108
7.3 Comparison to State-of-the-Art 114
7.4 Conclusions and Recommendations 117
7.5 Future Technical Trends 118
APPENDIX A: ERRORS DUE TO PROCESS VARIATIONS AND MISMATCH 120
v i
APPENDIX B: REDUCING ERRORS IN FOLDED-CASCODE TOPOLOGIES 123
APPENDIX C: DETERMINING THE MAGIC VOLTAGE 130
REFERENCES 132
VITA 142
vi i
LIST OF TABLES
Page
Table 1.1: Characteristics of SoC solutions and their impact on the design of bandgap
references. 9
Table 2.1: Comparison between simulation and analytical results for process-induced
error sources in bandgap references (at room temperature). 21
Table 2.2: Principle features of the various process-induced error sources in bandgap
references. 21
Table 2.3: Summary of various error sources in bandgap references. 33
Table 3.1: Offsets in bank of device pairs. 47
Table 3.2: Measured offsets of current-mirror pairs in a sample IC. 51
Table 3.3: Experimental offset performance of a single device pair with various width-to-
length dimensions. 53
Table 3.4: Minimum number of devices required to obtain a given mismatch
performance. 54
Table 5.1: Performance summary of the proposed low-impedance, sub-bandgap CMOS
reference (unless otherwise stated, V = 1.5V, T = 25°C, I = 0A). 79
DD A LOAD
Table 6.1: Measured offsets of pairs in bank of devices in one sample of one lot. 96
Table 7.1: List of contributions. 112
Table 7.2: Performance comparison against state-of-the-art. 116
Table B.1: Simulated circuit characteristics of folded cascode bandgap reference. 129

vi ii
LIST OF FIGURES
Page
Figure 1.1: Temperature behavior of a typical bandgap reference circuit. 2
Figure 1.2: Basic building block of bandgap reference circuits. 3
Figure 1.3: Concept of proposed system. 12
Figure 2.1: Basic bandgap reference cell and its process-induced error sources. 16
Figure 2.2: Comparison of simulated and analytical error in the reference voltage for (a)
resistor mismatch of 1%, (b) resistor tolerance of 20%, and (c) BJT mismatch
of 1%. 20
Figure 2.3: The variation of package with temperature for various samples [37]. 23
Figure 2.4: Cross-sectional images of (a) non-planarized, (b) planarized, and (c)
mechanically compliant layer dies [37]. 24
Figure 2.5: Block diagram of system using shunt feedback to regulate output voltage. 26
Figure 2.6: Intuitive impedance divider model for PSRR. 27
Figure 2.7: Simple model in action over a wide frequency range. 27
Figure 2.8: Effect of load variations on a reference. 30
Figure 2.9: Temperature variation of first-order bandgap reference. 32
Figure 3.1: Conventional CMOS bandgap reference. 35
Figure 3.2: Use of dynamic-element matching(DEM) to reduce mismatch offset errors.37
Figure 3.3: Block diagram of self-calibration strategies. 40
Figure 3.4: Block diagram of the Survivor strategy. 41
Figure 3.5: Schematic of comparator and sample switching sequence. 43
Figure 3.6: System diagram of the Survivor strategy. 46
Figure 3.7: Simulation results showing the digital code of the winner of each cycle with
convergence to Pair 101 (Pair 5). 47
Figure 3.8: Die photograph of prototype of Survivor strategy. 49
ix
Figure 3.9: Experimental test setup for prototype. 50
Figure 3.10: Experimental code and offset progression of the IC with the current-mirror
devices depicted in Table 6.2. 51
Figure 3.11: Statistical experimental offset performance of a single (6/0.6) pair and the
(6/0.6) survivor out of 32 pairs. 52
Figure 3.12: Statistical experimental offset performance of the Survivor scheme and a
series of single but larger geometry pairs (95% confidence interval). 53
Figure 3.13: Experimental offset performance of the survivor as a function of input
common-mode voltage (i.e., in the presence of bulk effects). 56
Figure 3.14: Schematic of an improved comparator whose resolution does not suffer from
bulk effects in the candidate pairs. 57
Figure 4.1: PSRR curve of a bandgap reference. 61
Figure 4.2: State-of the-art techniques to improve PSRR: (a) use of RC filters, (b) pre-
regulation, and (c) and (d) cascoding techniques. 62
Figure 4.3: Block diagram of proposed strategy for high PSRR. 64
Figure 4.4: Schematic of charge pump, bias for NMOS cascode, and RC filter. 65
Figure 4.5: Schematic of test low-dropout regulator. 66
Figure 4.6: Die photograph of high PSRR prototype IC. 67
Figure 4.7: Measured charge pump waveforms. 67
Figure 4.8: Measured line regulation of (a) crude reference for biasing cascode and (b)
core LDO regulator. 68
Figure 4.9: Measured PSRR performance without and with cascoding strategy. 69
Figure 4.10: Measured impact of cascode on LDO transient response. 70
Figure 5.1: Reported (a) current- and (b) hybrid-mode sub-bandgap approaches. 72
Figure 5.2: Reference-regulator low-impedance circuit and its adverse treatment of noise
and offset. 72
Figure 5.3: Block diagram of the proposed low-impedance sub-bandgap reference. 74
Figure 5.4: Measured and simulated (a) I vs. V vs. V and I vs. V curves for
C CE BE C BE
lateral PNP transistors. 75
x