Algo-Logic's Low Latency Library - Hot Interconnects

22 Pages·2012·1.41 MB·English

A Low Latency Library in FPGA Hardware
for High Frequency Trading (HFT)
John W. Lockwood, Adwait Gupte, Nishit Mehta
(Algo-Logic Systems)
Michaela Blott, Tom English, Kees Vissers
(Xilinx)

August 22, 2012, Santa Clara, CA
© Algo-Logic Systems Inc., All rights reserved

1
Outline
• Introduction
– High Frequency Trading (HFT)
• Survey of HFT Platforms
– Software, Hardware, and Hybrid Approaches
• Field Programmable Gate Arrays (FPGAs)
– Advantages and Disadvantages
• Algo-Logic’s Low Latency Library
– Implementation on NetFPGA 10G Platform
– Exposure and Position Tracking Application
– Protocols Supported
• Results

2
High Frequency Trading (HFT)
• HFT is
– Trading of equities, options, futures at high speed in
large volumes
– Earning money by exploiting the fleeting variation in
stock price or demand

• HFT accounts
– 70% of all trades in US Markets in 2010
– And it continues to grow

• HFT involves
– Using computers to place orders based on pre-defined
algorithms

3
Challenges in Financial Markets
Main Challenges

• Latency
– Execute orders faster than other investors to capture
fleeting variations in price and demand in the markets
• Jitter
– Provide consistent and fair executions
Secondary challenges
• Throughput
– Handle large volume of orders
• Flexibility
– Adapt to changing risks and trading strategies

4
Recent Problems in HFT
• Knightmare (Knight Capital)
– Test script executed live trades
– $450M loss in 45 minutes
• Nasdaq - Facebook IPO
– Order confirmations delayed
– $62M loss in direct damages
• BATS Failure
– Software bug in order auctions
– Forced to cancel IPO
Have not only hurt the banks/institutions
financially, but also the credibility of the market

5
Latency in Current Approaches
Software Hardware
• Linux 10GE NICs • Graphics Processor (GPU)
– 15-20 µs for Half-Round Trip – Optimized for throughput, but
Time (½ RTT) through not optimized for low latency
un-optimized kernel – Incurs additional overhead of
– TCP Offload: 2.9 µs Transmit + passing data through PCIe bus
6 µs Receive for ½ RTT
• ASIC
• Datagram Bypass Layer (DBL) – Achieves sub-µs latency
– 3.5 µs for UDP and – But lacks flexibility to handle
4.0 µs for TCP new protocols and features

• Infiniband MPI • FPGA
– 1 µs – Provides 0.2 µs latency w/TCP
(excluding application layer)
– Has the flexibility to support
new protocols and features

6
FPGA Approaches
Hybrid Computing Pure FPGA Computing
CPU + NIC + FPGA Offload FPGA handles all computing

• Unpredictable PCIe bus transfer • No bus copy
• Memory copy • No memory copy
• Potential cache misses • No cache misses
• Amdahl’s law • Parallel execution

7
FPGA outperforms Software
Latency
Jitter
• Hardware: 0.2 µs
• Hardware: 6 ns
• Software: 5 µs
• Software: 600 ns

8
Latency vs. Development Time
y
c
n
e
t
a
L Software on CPU
Higher Latency
Longer Development Time
FPGA
Lower Latency
Development Time
Hours Days Weeks Months Years
(Time to Market)
• Software solutions
– Require less development time to get started
• But FPGA hardware solutions achieve lower latency
– That fundamentally cannot be achieved with software

9
Algo-Logic’s Low Latency Library
• Infrastructure
• Market data in
local memory
• Protocol Parsers

Host PC Algo-Logic Platform

Stock Price Application Layer
no Host Application Tables (Custom Logic)
itare
cy
ilpaL
p
A
Algo-Logic C++ API Financial Protocol Parser Register Interface
k Networking Stack Session Datagram
rore
wteyaL OS Kernel IP Processing FPGA
N
k
niLre 10G 10G 10G 10G µBlaze SRAM
aya MAC MAC MAC MAC Soft Controller
taL CPU
D
lacisyreya CIN PHY PHY PHY PHY QSRDARM II
hL
P
10G Ethernet Links
Host (UDP) Broker Exchange

10