Advanced Digital System Design using SoC FPGAs. An Integrated Hardware/Software Approach

435 Pages·2023·12.589 MB·English

by  Ross K. Snider

Ross K. Snider
Advanced
Digital System
Design using
SoC FPGAs
An Integrated Hardware/Software Approach
Advanced Digital System Design using SoC FPGAs
Ross K. Snider
Advanced Digital System
Design using SoC FPGAs
An Integrated Hardware/Software Approach
RossK.Snider
MontanaStateUniversity
Bozeman,MT,USA
ISBN978-3-031-15415-7 ISBN978-3-031-15416-4 (eBook)
https://doi.org/10.1007/978-3-031-15416-4
©TheEditor(s)(ifapplicable)andTheAuthor(s),underexclusivelicensetoSpringerNatureSwitzerland
AG2023
Thisworkissubjecttocopyright.AllrightsaresolelyandexclusivelylicensedbythePublisher,whether
thewholeorpartofthematerialisconcerned,specificallytherightsoftranslation,reprinting,reuse
ofillustrations,recitation,broadcasting,reproductiononmicrofilmsorinanyotherphysicalway,and
transmissionorinformationstorageandretrieval,electronicadaptation,computersoftware,orbysimilar
ordissimilarmethodologynowknownorhereafterdeveloped.
Theuseofgeneraldescriptivenames,registerednames,trademarks,servicemarks,etc.inthispublication
doesnotimply,evenintheabsenceofaspecificstatement,thatsuchnamesareexemptfromtherelevant
protectivelawsandregulationsandthereforefreeforgeneraluse.
Thepublisher,theauthors,andtheeditorsaresafetoassumethattheadviceandinformationinthisbook
arebelievedtobetrueandaccurateatthedateofpublication.Neitherthepublishernortheauthorsor
theeditorsgiveawarranty,expressedorimplied,withrespecttothematerialcontainedhereinorforany
errorsoromissionsthatmayhavebeenmade.Thepublisherremainsneutralwithregardtojurisdictional
claimsinpublishedmapsandinstitutionalaffiliations.
ThisSpringerimprintispublishedbytheregisteredcompanySpringerNatureSwitzerlandAG
Theregisteredcompanyaddressis:Gewerbestrasse11,6330Cham,Switzerland
Tomylovingfamily
MywifeKimberley,
MysonsAndrewandChristopher,
MydaughtersAshleighandEmily.
Preface
Thistextbookaroseoutofmyexperiencesteachingcomputerengineeringandelec-
tricalengineeringcoursesatMontanaStateUniversity(MSU).FieldProgrammable
Gate Arrays (FPGAs) are digital devices that have been around since the 1980s
andareaccessibletostudents,allowingthemtocreatetheirowncustomhardware
withouttheprohibitiveexpenseofcreatingacustomASICordigitalchip.FPGAs
startedastinydeviceswheretheyfunctionedas“glue”logic,buttheyhavegrown
to be among the largest digital devices today. As FPGAs grew larger, they started
absorbing all sorts of logic functions, including a complete ARM based computer
system, i.e., a System-on-Chip (SoC). SoC FPGAs are ideal devices for teaching
computerengineeringsinceinthesamechipyoucancreatecustomhardwareinthe
FPGAfabricanddevelopsoftwarethatrunsontheARMCPUs.Thisallowsstudents
togainasystemlevelunderstandingofhowcomputerswork.Theygainthissystem
level knowledge by first creating their own custom hardware in the FPGA fabric
andthencontrollingtheirhardwarebywritingaLinuxdevicedriverandassociated
applicationsoftware.Ithasbeenquitesatisfyingseeingtheexcitementinstudent’s
faceswhentheyfinallyunderstandhowhardwareandsoftwareinteract.
IalsoteachtheDigitalSignalProcessingcourseatMSU,andFPGAsandDSP
go well together. DSP is an important application area of FPGAs, and the highest
performing DSP is done in FPGAs. This is because there can be thousands of
multipliersrunninginparallelintheFPGAfabric.Notonlythat,theprogrammable
I/OofFPGAsallowdatatobepipeddirectlytotheFPGAfabric,getprocessed,and
thenpipeddirectlybackout.Thisallowsthesedevicestohavethelowestprocessing
latencyofanydigitaldevice.FPGAshavelowerprocessinglatencythanCPUsand
GPUsduetothiscustomI/O.
The focus on audio signal processing is a result of my background in auditory
neuroscience. Before coming to MSU, I completed a postdoctoral fellowship at
JohnsHopkinsUniversityintheLaboratoryofAuditoryNeurophysiologyunderthe
direction of Xiaoqin Wang. Thus I’m interested in how the brain processes sound
andofcoursethepracticalaspectsofaudioprocessingusingFPGAs.Theprocessing
and bandwidth requirements of audio processing fit well within the constraints of
thelow-costCycloneVSoCFPGAfamily,makingaudioprocessinganaccessible
vii
viii Preface
application area for students. A NIH grant for creating a platform for open speech
signal processing was instrumental in developing the audio board targeted in the
book.Thusanaturaloutcomewastohavestudentscreatetheirownreal-timesound
effectsprocessor.Thishasbeenverymotivatingforstudents.
TheculminationofmyexperiencesinFPGAs,DSP,auditoryneuroscience,and
teaching is this textbook. It is an integrated hardware/software approach to audio
signal processing using SoC FPGAs. SoC FPGAs allow the merging of what has
typicallybeenthesiloedareasofcomputerhardwareandsoftware.Thistextbookis
myattemptatmergingthesetwoareaswhilecreatinganaudiosystemthatstudents
havefuncreatingandplayingwith.
MontanaStateUniversity
Bozeman,Montana
RossK.Snider
July1,2022
Acknowledgments
IwouldliketothankTrevorVannoywhohelpedcreatesomeofthelabandLinux
material. Trevor was very good and helpful on the Linux front and helped many
studentsdebugtheirsystems.
IwouldliketothankthosewhohadapartindevelopingtheAudioMiniboard
that was funded by NIH (grant 1R44DC01544301). Ray Weber for the analog in-
terfacing and initial Linux device driver development. Connor Dack for the PCB
boardrefinementthatwaswelllaidout.ChrisCasebeer,TylerDavis,andWillTidd
forhelpingtomanagethehardwareprojectandfixingsomeoftheearlierhardware
issues.DougRobertsandGrahamConranwhoprovidedtheSensorLogicbusiness
thatisthehomefortheAudioMiniboard.
Finally,IwouldliketothankthestudentsinmyFPGAcoursesfortryingoutnew
materialthatdidn’talwaysgoasplannedandwhoprovidedgreatfeedback.
ix
Contents
PartI Introductions
1 Preliminaries .................................................. 3
1.1 AboutThisBook........................................... 3
1.1.1 GitHubRepository................................... 4
1.2 WhyLearnAboutSoCFPGAs? .............................. 4
1.2.1 FurtherReading ..................................... 7
1.3 Prerequisites............................................... 7
1.3.1 PriorHardwareKnowledge............................ 7
1.3.2 PriorSoftwareKnowledge............................. 8
1.4 HardwareNeeded .......................................... 8
1.4.1 Laptop ............................................. 9
1.4.2 DE10-NanoFPGABoard ............................. 9
1.4.3 AudioBoard ........................................ 10
1.4.4 MiscellaneousHardware .............................. 10
1.5 SoftwareNeeded ........................................... 12
1.6 TheDevelopmentLandscape................................. 13
References ..................................................... 14
2 IntroductiontoSystem-on-ChipFieldProgrammableGateArrays .. 17
2.1 TheDigitalRevolution ...................................... 17
2.2 BasicFPGAArchitecture.................................... 19
2.2.1 ExternalI/O ........................................ 20
2.2.2 LogicElements...................................... 20
2.2.3 Memory............................................ 20
2.2.4 DSPBlocks......................................... 20
2.3 SoCFPGAArchitecture..................................... 22
References ..................................................... 23
xi
xii Contents
3 IntroductiontotheSoCFPGABootProcess ...................... 25
3.1 CycloneVSoCFPGABootProcess........................... 25
3.1.1 BootStep1:Power-UporReset ........................ 26
3.1.2 BootStep2:BootROM............................... 26
3.1.3 BootStep3:Preloader................................ 28
3.1.4 BootStep4:U-boot .................................. 29
3.1.5 BootStep5:Linux ................................... 30
3.1.6 BootStep6:Application .............................. 30
References ..................................................... 30
4 IntroductiontotheDE10-NanoBoard ........................... 33
4.1 DE10-NanoBoard.......................................... 33
4.1.1 DeterminingDE10-NanoBoardRevision ................ 34
4.1.2 DE10-NanoInformation .............................. 34
4.1.3 DE10-NanoCycloneVSoCFPGA ..................... 34
4.1.4 DE10-NanoConfigurationModeSwitchSetting .......... 35
References ..................................................... 39
5 IntroductiontotheAudioMiniBoard ............................ 41
5.1 TopLevelBlockDiagram.................................... 42
5.2 AnalogAudioInput......................................... 43
5.3 AD1939AudioCodec....................................... 44
5.3.1 AD1939SerialDataPort.............................. 47
5.3.2 AD1939SPIControlPort ............................. 48
5.4 HeadphoneAnalogAudioOutput ............................. 50
5.4.1 TPA6130A2I2CInterface............................. 51
5.5 DE10-NanoFPGAConnections .............................. 52
References ..................................................... 53
6 IntroductiontoIntelQuartusPrime ............................. 55
6.1 IntelQuartusPrimeLiteEdition .............................. 55
6.1.1 InstallingWindowsforSubsystemforLinux(WSL) ....... 55
6.1.2 DownloadandInstallIntel’sQuartusPrimeLite .......... 56
6.1.3 QuartusFileTypes ................................... 56
6.1.4 ConvertingProgrammingFiles......................... 58
6.1.5 Timing............................................. 58
6.1.6 LearningQuartus .................................... 60
6.2 PlatformDesigner .......................................... 62
6.2.1 CreatinganAvalonMemory-MappedInterface ........... 62
6.2.2 CreatingaCustomPlatformDesignerComponent......... 65
6.2.3 CreatinganAvalonStreamingInterface ................. 69
6.3 SystemConsole............................................ 69
6.3.1 TheGeneralFlowforUsingSystemConsole ............. 70
6.3.2 ModifyingtheDesigninPlatformDesigner .............. 71
6.3.3 UsingSystemConsole................................ 72