56Gs/s ADC Enabling 100GbE

28 Pages·2010·0.82 MB·English

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Ian Dedic, Chief Engineer, Fujitsu Microelectronics Europe
OFC2010 Invited Paper, Digital Transmission Systems
Copyright 2009 FUJITSU MICROELECTRONICS EUROPE GmbH
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100G coherent receiver
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Why single-chip CMOS?
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So what is so difficult?
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CHAIS ADC
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DSP and integration
(cid:1)
Package and PCB
(cid:1)
Testing
(cid:1)
Examples
(cid:1)
Future challenges
OFC2010/OThT6 -- 56 GS/s ADC: Enabling 100GbE 1 Fujitsu Microelectronics Europe -http://www.chais.info
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OFC2010/OThT6 -- 56 GS/s ADC: Enabling 100GbE 2 Fujitsu Microelectronics Europe -http://www.chais.info
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4-channel 56Gs/s ADC, minimum 6b resolution
(cid:1) DP-QPSK receiver with H/V channels, I/Q conversion (OIF standard)
(cid:1) 2x oversampling minimizes impact on performance
• 56Gs/s needed, >60Gs/s with soft FEC
(cid:1) In early 2009, predicted availability for such an ADC was in 2013
• Major obstacle to target rollout date for 100G networks
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DSP to remove transmission channel imperfections and recover data
(cid:1) Dispersion, cross-polarization, time-varying channel, clock recovery
(cid:1) ~12 TeraOperations/sec (TOPS) for 40Gb/s (cid:2) ~30 TOPS for 100Gb/s ?
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Power consumption and thermal constraints
(cid:1) OIF target for complete coherent transponder ~70W
(cid:1) Severe challenge for both ADC and DSP design
• Total power for ADC+DSP needs to be < 50W
(cid:1) Environmental restrictions make problem even more difficult than it first appears
OFC2010/OThT6 -- 56 GS/s ADC: Enabling 100GbE 3 Fujitsu Microelectronics Europe -http://www.chais.info
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Massive data bandwidth between ADC and DSP
(cid:1) 4-channel 6-8b 56Gs/s ADC means 1.3-1.8Tb/s of data at interface
(cid:1) Getting this from one chip to another costs power and chip area
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• 10G SERDES link ~100mW/channel 3-4W per ADC
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Critical performance factor is power efficiency, not just speed
(cid:1) Discrete ADC dissipating >10W each are difficult to use
• Total power dissipation is too high (>100W)
• Skew management/calibration nightmare (especially over temperature/lifetime)
• Higher intrinsic manufacturing cost and lower yield for a hybrid
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Single-chip CMOS solution is the “Holy Grail”
(cid:1) Integrate on ASIC with >50M gates (limited by power dissipation)
(cid:1) Leverage CMOS technology advances to drive down power and cost
• Single-chip allows integration of calibration and channel deskew/matching
(cid:1) ADC and DAC get faster and lower power at the same rate as digital – ideally ☺
OFC2010/OThT6 -- 56 GS/s ADC: Enabling 100GbE 4 Fujitsu Microelectronics Europe -http://www.chais.info
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ADC is the biggest circuit design problem
(cid:1) Ultra-high speed, low noise and jitter, low power consumption – all same time
(cid:1) Conventional techniques cannot easily deliver required performance
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Digital-analogue noise coupling
(cid:1) Sampler/clock jitter <100fs on same chip as DSP with >100A current spikes
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Wide bandwidth (>15GHz), good S11 (up to >30GHz), low theta-jc
(cid:1) Sampler, package, PCB design all very challenging
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DSP design is out-of-the-ordinary (tens of TeraOPS)
(cid:1) Extremely power-efficient (cid:2) use massive parallelism, not GHz clocks
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Test
(cid:1) Performance verification challenges limits of test equipment
(cid:1) Need at-speed performance verification in production, not just functional testing
OFC2010/OThT6 -- 56 GS/s ADC: Enabling 100GbE 5 Fujitsu Microelectronics Europe -http://www.chais.info
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Wideband low-noise sampler + demultiplexer + interleaved ADC array
(cid:1) Smaller CMOS geometries (cid:2) higher speed (cid:2) worse mismatch and noise
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Single 56Gs/s track/hold very difficult due to extreme speed
(cid:1) <9ps to acquire, <9ps to transfer to following interleaved T/H stages
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Interleaved track/hold (e.g. 4-channel 14Gs/s) also very difficult
(cid:1) Signal/clock delays must match to <<1ps – how do you measure this?
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Noise, mismatch and power of cascaded circuits all adds up
(cid:1) Multiple sampling capacitors, buffers, switches, demultiplexers…
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Interleaved ADC back-end is not so difficult (but only in comparison!)
(cid:1) Design for best power and area efficiency rather than highest speed
(cid:1) Interleave as many as necessary to achieve required sampling rate
(cid:1) 8 x 175Ms/s 8b SAR ADCs fit underneath 1 solder bump (cid:2) 45Gs/s per sq mm ☺
OFC2010/OThT6 -- 56 GS/s ADC: Enabling 100GbE 6 Fujitsu Microelectronics Europe -http://www.chais.info
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CHArge-mode Interleaved Sampler (CHAIS)
DEMUX
14GHz VCO
80 x ADC Inputs 80 x 8b ADC Outputs
(1 per ADC pair)
Clocks
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Trim Voltages
Calibration
OFC2010/OThT6 -- 56 GS/s ADC: Enabling 100GbE 7 Fujitsu Microelectronics Europe -http://www.chais.info
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OFC2010/OThT6 -- 56 GS/s ADC: Enabling 100GbE 8 Fujitsu Microelectronics Europe -http://www.chais.info
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56Gs/s with 8 bit resolution
(cid:1) Extra resolution allows some digital AGC after ADC instead of in OFE
• Non-ideal INL/DNL has negligible impact on performance
(cid:1) 63Gs/s for 40nm ADC to allow for higher overhead soft decision FEC
• Higher clock rate plus soft FEC needs 40nm to meet same power budget
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16GHz bandwidth
(cid:1) Closely controlled, can be extended using digital equalization if required
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ENOB>5.7 for -6dBFS sinewave input
(cid:1) Similar power to 100G OFE output signal peaking at full-scale (PAR=9dB)
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ENOB almost constant with input frequency
(cid:1) On-chip PLL jitter is 30fs rms, THD < -40dBc at 15GHz
(cid:1) <0.2ENOB variation from 1GHz to 15GHz
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Power consumption 2W per ADC in 65nm, 9W for complete 4-channel RX
(cid:1) 5W for 63Gs/s 40nm 4-channel RX – power scales better than digital !
OFC2010/OThT6 -- 56 GS/s ADC: Enabling 100GbE 9 Fujitsu Microelectronics Europe -http://www.chais.info