3Chan,16Bit, 45MSPS Dig Copier Ana Frt End w/Inte Sens Tim Gen & LVDS Out

114 Pages·2014·6.78 MB·English

LM98714
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LM98714 Three Channel, 16-Bit, 45 MSPS Analog Front End with LVDS/CMOS Output and
Integrated CCD/CIS Sensor Timing Generator
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FEATURES DESCRIPTION
1
• LVDS/CMOSOutputs The LM98714 is a fully integrated, high performance
2 16-Bit, 45 MSPS signal processing solution for digital
• LVDS/CMOSPixelRateInputClockor ADC
color copiers, scanners, and other image processing
Input Clock
applications. High-speed signal throughput is
• CDSorS/HProcessingforCCDor CIS achieved with an innovative architecture utilizing
Sensors Correlated Double Sampling (CDS), typically
employed with CCD arrays, or Sample and Hold
• IndependentGain/OffsetCorrectionforEach
(S/H) inputs (for Contact Image Sensors and CMOS
Channel
image sensors). The signal paths utilize 8 bit
• Digital BlackLevelCorrectionLoop forEach Programmable Gain Amplifiers (PGA), a ±9-Bit offset
Channel correction DAC and independently controlled Digital
• ProgrammableInputClampVoltage Black Level correction loops for each input. The PGA
and offset DAC are programmed independently
• FlexibleCCD/CISSensorTimingGenerator
allowing unique values of gain and offset for each of
the three inputs. The signals are then routed to a
APPLICATIONS
45MHz high performance analog-to-digital converter
• Multi-Function Peripherals (ADC). The fully differential processing channel
shows exceptional noise immunity, having a very low
• FacsimileEquipment
noise floor of –74dB. The 16-bit ADC has excellent
• Flatbed orHandheldColor Scanners dynamic performance making the LM98714
• High-SpeedDocumentScanner transparentintheimagereproductionchain.
CCD/CIS Sensor
KEY SPECIFICATIONS
Analog Front End
SPI
• MaximumInputLevel:1.2or 2.4VoltModes
– (Both with+or -PolarityOption)
LM98714 Image Processor/ASIC
• ADCResolution:16-Bit Data Output
• ADCSampling Rate:45MSPS Motor
Sensor Drivers CGCeDn eTrimationrg Controllers
• INL:±23LSB(Typ)
• ChannelSampling Rate:15/22.5/30MSPS Figure1. SystemBlockDiagram
• PGAGain Steps:256Steps
• PGAGain Range:0.7to7.84x
• AnalogDACResolution: ±9Bits
• AnalogDACRange: ±300mVor±600mV
• Digital DACResolution: ±6Bits
• Digital DACRange:-1024LSBto+1008LSB
• SNR: -74dB(@0dBPGAGain)
• PowerDissipation:505mW(LVDS)610mW
(CMOS)
• OperatingTemp:0to70°C
• SupplyVoltage:3.3VNominal(3.0Vto3.6V
Range)
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof
TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
Alltrademarksarethepropertyoftheirrespectiveowners.
2
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2006–2014,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
LM98714
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LM98714 Overall Chip Block Diagram
Figure2. ChipBlockDiagram
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LM98714 Pin Out Diagram
CLK3 1 48 CLK4
CLK2 2 47 VC
CLK1 3 46 DGND
SH 4 45 CLK5
RESET 5 44 CLK6
SH_R 6 43 CLK7
SDIO 7 42 CLK8
SCLK 8 41 CLK9
SEN 9 40 CLKOUT/CLK10
AGND 10 39 VD
VA 11 38 DGND
VREFB 12 48 Pin TSSOP 37 DOUT0/TXOUT0-
(not to scale)
VREFT 13 36 DOUT1/TXOUT0+
VA 14 35 DOUT2/TXOUT1-
AGND 15 34 DOUT3/TXOUT1+
VCLP 16 33 DOUT4/TXOUT2-
VA 17 32 DOUT5/TXOUT2+
AGND 18 31 DOUT6/TXCLK-
OSR 19 30 DOUT7/TXCLK+
AGND 20 29 INCLK-
OSG 21 28 INCLK+
AGND 22 27 DVB
OSB 23 26 VR
AGND 24 25 DGND
Figure3. LM98714PinOutDiagram
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Typical Application Diagram
5 4 3 2 1
D D
Serial Interface and device controlbus
Flexible CCDTiming Gener atorOutputs
+3.3V
C CDCrivDe rC(slo)ck CCSCHLLLKKK213123456789 CCCSRSSSSDHHECELLLKKKNI_SLOR321KET LM987C1L4KOUT_CDCCCCCCLGKLLLLLLNVKKKKKK1DC0987654 444444444601234578 CCCCCCCLLLLLLLKKKKKKK45678910+3.3V 0.1uF +3.3V4.7uF Connector RCiabbbloen Connector C
ISCImnelpoanucgstkesor 0.10u.F1uF0.10u.F1uF0.10u.F1uF 1111111112345670 AVVVVAVVAAAGGRRCEELNNPFFDDBT DDDDDD531D420D___7___6TTT_TTT_XXXTXXXTOOOXOOOXDCUUUCUUUGLTTTLTTTNVK210K210DD++++---- 33333333338012345769 0.1uF ** TTTTTTTTXXXXXXXXOOOCCOOOLLUUUUUUKKTTTTTT+-102012+++--- LD(oDVre SDes9qeS0uriCiavl.R)2i1z8eAr ASIC
+3.3V *R_cmos_clk
B 11222228901234 AOAOAOAGGGGSSSNgNbNNrDDDD IINNDCCGDLLNVVKKDRB+- 2222256789 0.1+u3F.3V 0.1uF*R10_0lvOdsh_mclk 0Ohm IINNCCLLKK+-** CLOCK Gen B
CCD or CIS
Image Sensor
* If using an LVDS input clock, temi nateclockatthe
pins with a 100 Ohm resistor and rem ove0Ohmresistor
from INCLK- to ground.
If using a CMOS input clock, short theINCLK-pinto
ground and remove the 100 Ohm L VDStermination
resistor.
A A
** Maintain 100 Ohm Impedance for all LVDSdifferential NationalSemiconductorCorporation
pair paths. EastCoastLabsDesignCenter
Title
LM98714TypicalApplicationDiagram
Size DocumentNumber Rev
B <Doc> A
Date: Friday,January27,2006 Sheet 1 of 1
5 4 3 2 1
Figure4. Typical ApplicationDiagram
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PINDESCRIPTIONS(1)
Pin Name I/O Typ Res Description
1 CLK3 O D PU Configurablesensorcontroloutput.
2 CLK2 O D PD Configurablesensorcontroloutput.
3 CLK1 O D PU Configurablesensorcontroloutput.
4 SH O D PD Sensor-ShiftortransfercontrolsignalforCCDandCISsensors.
5 RESET I D PU Active-lowmasterreset.NCwhenfunctionnotbeingused.
6 SH_R I D PD ExternalrequestforanSHpulse.
7 SDIO I/O D SerialInterfaceDataInput
8 SCLK I D PD SerialInterfaceshiftregisterclock.
9 SEN I D PU Active-lowchipenablefortheSerialInterface.
10 AGND P Analoggroundreturn.
11 V P Analogpowersupply.Bypassvoltagesourcewith4.7μFandpinwith0.1μFtoAGND.
A
12 VREFB O A BottomofADCreference.Bypasswitha0.1μFcapacitortoground.
13 VREFT O A TopofADCreference.Bypasswitha0.1μFcapacitortoground.
14 V P Analogpowersupply.Bypassvoltagesourcewith4.7μFandpinwith0.1μFtoAGND.
A
15 AGND P Analoggroundreturn.
16 VCLP IO A InputClampVoltage.Normallybypassedwitha0.1μF,anda4.7μFcapacitortoAGND.
Anexternalreferencevoltagemaybeappliedtothispin.
16 VCLP IO A InputClampVoltage.Normallybypassedwitha0.1μF,anda10μFcapacitortoAGND.
Anexternalreferencevoltagemaybeappliedtothispin.
17 V P Analogpowersupply.Bypassvoltagesourcewith4.7μFandpinwith0.1μFtoAGND.
A
18 AGND P Analoggroundreturn.
19 OS I A Analoginputsignal.TypicallysensorRedoutputAC-coupledthruacapacitor.
R
20 AGND P Analoggroundreturn.
21 OS I A Analoginputsignal.TypicallysensorGreenoutputAC-coupledthruacapacitor.
G
22 AGND P Analoggroundreturn.
23 OS I A Analoginputsignal.TypicallysensorBlueoutputAC-coupledthruacapacitor.
B
24 AGND P Analoggroundreturn.
25 DGND P Digitalgroundreturn.
26 V P Powersupplyinputforinternalvoltagereferencegenerator.Bypassthissupplypinwitha
R
0.1μFcapacitor.
27 DVB O D DigitalCoreVoltagebypass.Notaninput.Bypasswith0.1μFcapacitortoDGND.
28 INCLK+ I D ClockInput.Non-InvertinginputforLVDSclocksorCMOSclockinput.CMOSclockis
selectedwhenpin29isheldatDGND,otherwiseclockisconfiguredforLVDSoperation.
29 INCLK- I D ClockInput.InvertinginputforLVDSclocks,connecttoDGNDforCMOSclock.
30 DOUT7/ O D Bit7ofthedigitalvideooutputbusinCMOSMode,LVDSFrameClock+inLVDSMode.
TXCLK+
31 DOUT6/ O D Bit6ofthedigitalvideooutputbusinCMOSMode,LVDSFrameClock-inLVDSMode.
TXCLK-
32 DOUT5/ O D Bit5ofthedigitalvideooutputbusinCMOSMode,LVDSDataOut2+inLVDSMode.
TXOUT2+
33 DOUT4/ O D Bit4ofthedigitalvideooutputbusinCMOSMode,LVDSDataOut2-inLVDSMode.
TXOUT2-
34 DOUT3/ O D Bit3ofthedigitalvideooutputbusinCMOSMode,LVDSDataOut1+inLVDSMode.
TXOUT1+
35 DOUT2/ O D Bit2ofthedigitalvideooutputbusinCMOSMode,LVDSDataOut1-inLVDSMode.
TXOUT1-
(1) (I=Input),(O=Output),(IO=Bi-directional),(P=Power),(D=Digital),(A=Analog),(PU=PullUpwithaninternalresistor),(PD=PullDown
withaninternalresistor.).
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PINDESCRIPTIONS(1)(continued)
Pin Name I/O Typ Res Description
36 DOUT1/ O D Bit1ofthedigitalvideooutputbusinCMOSMode,LVDSDataOut0+inLVDSMode.
TXOUT0+
37 DOUT0/ O D Bit0ofthedigitalvideooutputbusinCMOSMode,LVDSDataOut0-inLVDSMode.
TXOUT0-
38 DGND P Digitalgroundreturn.
39 V P Powersupplyforthedigitalcircuits.Bypassthissupplypinwith0.1μFcapacitor.Asingle
D
4.7μFcapacitorshouldbeusedbetweenthesupplyandtheVD,VRandVCpins.
40 CLKOUT/ O D PD OutputclockforregisteringoutputdatawhenusingCMOSoutputs,orconfigurable
CLK10 sensorcontroloutput.
41 CLK9 O D PD Configurablesensorcontroloutput.
42 CLK8 O D PD Configurablesensorcontroloutput.
43 CLK7 O D PD Configurablesensorcontroloutput.
44 CLK6 O D PU Configurablesensorcontroloutput.
45 CLK5 O D PD Configurablesensorcontroloutput.
46 DGND P Digitalgroundreturn.
47 V P Powersupplyforthesensorcontroloutputs.Bypassthissupplypinwith0.1μFcapacitor.
C
48 CLK4 O D PD Configurablesensorcontroloutput.
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Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam
duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
Absolute Maximum Ratings(1)(2)
SupplyVoltage(VA,VR,VD,VC) 4.2V
VoltageonAnyInputPin(Nottoexceed4.2V)(3) −0.3Vto(VA+0.3V)
VoltageonAnyOutputPin(execptDVBandnottoexceed4.2V) −0.3Vto(VA+0.3V)
DVBOutputPinVoltage 2.0V
InputCurrentatanypinotherthanSupplyPins(4) ±25mA
PackageInputCurrent(exceptSupplyPins)(4) ±50mA
MaximumJunctionTemperature(T ) 150°C
A
ThermalResistance(θ ) 66°C/W
JA
PackageDissipationatT =25°C(5) 1.89W
A
HumanBodyModel 2500V
ESDRating(6)
MachineModel 250V
StorageTemperature −65°Cto+150°C
SolderingprocessmustcomplywithTexasInstruments’ReflowTemperatureProfilespecifications.Refertowww.ti.com/packaging(7)
(1) AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.OperatingRatingsindicateconditionsfor
whichthedeviceisfunctional,butdonotensurespecificperformancelimits.Forensuredspecificationsandtestconditions,seethe
ElectricalCharacteristics.Theensuredspecificationsapplyonlyforthetestconditionslisted.Someperformancecharacteristicsmay
degradewhenthedeviceisnotoperatedunderthelistedtestconditions.OperationofthedevicebeyondtheOperatingRatingsisnot
recommended.
(2) AllvoltagesaremeasuredwithrespecttoAGND=DGND=0V,unlessotherwisespecified.
(3) Theanaloginputsareprotectedasshownbelow.Inputvoltagemagnitudesbeyondthesupplyrailswillnotdamagethedevice,provided
thecurrentislimitedpernote3.However,inputerrorswillbegeneratedIftheinputgoesaboveVAandbelowAGND.
VA
I/O
To Internal Circuitry
AGND
(4) Whentheinputvoltage(V )atanypinexceedsthepowersupplies(V <GNDorV >V orV ),thecurrentatthatpinshouldbe
IN IN IN A D
limitedto25mA.The50mAmaximumpackageinputcurrentratinglimitsthenumberofpinsthatcansimultaneouslysafelyexceedthe
powersupplieswithaninputcurrentof25mAtotwo.
(5) ThemaximumpowerdissipationmustbederatedatelevatedtemperaturesandisdictatedbyT ,θ andtheambienttemperature,
JMAX JA
T .ThemaximumallowablepowerdissipationatanytemperatureisP =(T –T )/θ .Thevaluesformaximumpowerdissipation
A D JMAX A JA
listedabovewillbereachedonlywhenthedeviceisoperatedinaseverefaultcondition(forexample,wheninputoroutputpinsare
drivenbeyondthepowersupplyvoltages,orthepowersupplypolarityisreversed).Suchconditionsshouldalwaysbeavoided.
(6) Humanbodymodelis100pFcapacitordischargedthrougha1.5kΩresistor.Machinemodelis220pFdischargedthrough0Ω.
(7) Reflowtemperatureprofilesaredifferentforlead-freeandnon-lead-freepackages.
Operating Ratings(1)(2)
OperatingTemperatureRange 0°C≤T ≤+70°C
A
AllSupplyVoltage +3.0Vto+3.6V
(1) AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.OperatingRatingsindicateconditionsfor
whichthedeviceisfunctional,butdonotensurespecificperformancelimits.Forensuredspecificationsandtestconditions,seethe
ElectricalCharacteristics.Theensuredspecificationsapplyonlyforthetestconditionslisted.Someperformancecharacteristicsmay
degradewhenthedeviceisnotoperatedunderthelistedtestconditions.OperationofthedevicebeyondtheOperatingRatingsisnot
recommended.
(2) AllvoltagesaremeasuredwithrespecttoAGND=DGND=0V,unlessotherwisespecified.
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Electrical Characteristics
ThefollowingspecificationsapplyforVA=VD=VR=VC=3.3V,C =10pF,andf =15MHzunlessotherwisespecified.
L INCLK
BoldfacelimitsapplyforT =T toT ;allotherlimitsT =25°C.
A MIN MAX A
Symbol Parameter Conditions Min Typ(1) Max Units
CMOSDigitalInputDCSpecifications(RESETb,SH_R,SCLK,SENb)
V Logical“1”InputVoltage 2.0 V
IH
V Logical“0”InputVoltage 0.8 V
IL
V =VD
IH
RESET 235 nA
I Logical“1”InputCurrent
IH
SH_R,SCLK 70 μA
SEN 130 nA
VIL=DGND
RESET 70 μA
I Logical“0”InputCurrent
IL
SH_R,SCLK 235 nA
SEN 70 μA
CMOSDigitalOutputDCSpecifications(SH,CLK1toCLK10,CMOSDataOutputs)
V Logical“1”OutputVoltage I =-0.5mA 2.95 V
OH OUT
V Logical“0”OutputVoltage I =1.6mA 0.25 V
OL OUT
V =DGND 16
OUT
I OutputShortCircuitCurrent mA
OS
V =VD -20
OUT
V =DGND 20
OUT
I CMOSOutputTRI-STATECurrent nA
OZ
V =VD -25
OUT
CMOSDigitalInput/OutputDCSpecifications(SDIO)
I Logical“1”InputCurrent V =VD 90 nA
IH IH
I Logical“0”InputCurrent V =DGND 90 nA
IL IL
LVDS/CMOSClockReceiverDCSpecifications(INCLK+andINCLK-Pins)
DifferentialLVDSClock
V 100 mV
IHL HighThresholdVoltage R =100W,V (LVDSInput
L CM
DifferentialLVDSClock CommonModeVoltage)=1.25V
V -100 mV
ILL LowThresholdVoltage
CMOSClock
V 2.0 V
IHC HighThresholdVoltage
INCLK-=DGND
CMOSClock
V 0.8 V
ILC LowThresholdVoltage
I CMOSClockInputHighCurrent 280 μA
IHL
I CMOSClockInputLowCurrent -150 μA
ILC
LVDSOutputDCSpecifications
V DifferentialOutputVoltage 180 328 450 mV
OD
R =100Ω
L
V LVDSOutputOffsetVoltage 1.17 1.23 1.3 V
OS
I OutputShortCircuitCurrent V =0V,R =100Ω 7.9 mA
OS OUT L
(1) TypicalfiguresareatT =25°C,andrepresentmostlikelyparametricnormsatthetimeofproductcharacterization.Thetypical
A
specificationsarenotensured.
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Electrical Characteristics (continued)
ThefollowingspecificationsapplyforVA=VD=VR=VC=3.3V,C =10pF,andf =15MHzunlessotherwisespecified.
L INCLK
BoldfacelimitsapplyforT =T toT ;allotherlimitsT =25°C.
A MIN MAX A
Symbol Parameter Conditions Min Typ(1) Max Units
PowerSupplySpecifications
VANormalState 60 97 125
IA VAAnalogSupplyCurrent VALowPowerState mA
12 23 32
(Powerdown)
VRNormalState
30 64 75 mA
(LVDSOutputs)
IR VRDigitalSupplyCurrent CMOSOutputDataFormat 15 47 55 mA
LVDSOutputDataFormatwith
47 mA
DataOutputsDisabled
LVDSOutputDataFormat 0.05 mA
ID VDDigitalOutputDriverSupply CMOSOutputDataFormat
Current (ATELoadingofCMOSOutputs 12 40 mA
>50pF)
Typicalsensoroutputs:SH,
CLK1=Φ1A,CLK2=Φ2A,
VCCCDTimingGeneratorOutput CLK3=ΦB,CLK4=ΦC,
IC 0.5 12 mA
DriverSupplyCurrent CLK5=RS,CLK6=CP
(ATELoadingofCMOSOutputs
>50pF)
LVDSOutputDataFormat 350 505 650 mW
PWR AveragePowerDissipation CMOSOutputDataFormat(ATE
LoadingofCMOSOutputs> 380 610 700 mW
50pF)
InputSamplingCircuitSpecifications
CDSGain=1x,PGAGain=1x 2.3
V InputVoltageLevel Vp-p
IN
CDSGain=2x,PGAGain=1x 1.22
SourceFollowersOff 50 70
CDSGain=1x μA
OS =VA(OS =AGND) (-70) (-40)
X X
SourceFollowersOff 75 105
SampleandHoldModeInputLeakage
I CDSGain=2x μA
IN_SH Current OS =VA(OS =AGND) (-105) (-75)
X X
SourceFollowersOn -10
CDSGain=2x -200 200 nA
OS =VA(OS =AGND) -16
X X
Sample/HoldMode CDSGain=1x 2.5
C EquivalentInputCapacitance pF
SH
(seeFigure12) CDSGain=2x 4
SourceFollowersOff 7
I CDSModeInputLeakageCurrent -300 300 nA
IN_CDS OSX=VA(OSX=AGND) (-25)
CLPINSwitchResistance
R 16 50 Ω
CLPIN (OS toVCLPNodeinFigure9)
X
VCLPReferenceCircuitSpecifications
VCLPDACResolution 4 Bits
VCLPDACStepSize 0.16 V
VCLPConfig.
VCLPDACVoltageMinOutput 0.14 0.26 0.43 V
Register=00010000b
VCLPConfig.
V VCLPDACVoltageMaxOutput 2.38 2.68 2.93 V
VCLP Register=00011111b
VCLPConfig.
ResistorLadderEnabled 1.54 V /2 1.73 V
Register=0010xxxxb A
VCLPDACShortCircuitOutput VCLPConfig.
I 30 mA
SC Current Register=0001xxxxb
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Electrical Characteristics (continued)
ThefollowingspecificationsapplyforVA=VD=VR=VC=3.3V,C =10pF,andf =15MHzunlessotherwisespecified.
L INCLK
BoldfacelimitsapplyforT =T toT ;allotherlimitsT =25°C.
A MIN MAX A
Symbol Parameter Conditions Min Typ(1) Max Units
BlackLevelOffsetDACSpecifications
Resolution 10 Bits
Monotonicity Ensuredbycharacterization
CDSGain=1x
-614
MinimumDACCode=0x000 mV
OffsetAdjustmentRangeReferredto MaximumDACCode=0x3FF 614
AFEInput CDSGain=2x
-307
MinimumDACCode=0x000 mV
MaximumDACCode=0x3FF 307
OffsetAdjustmentRangeReferredto MinimumDACCode=0x000 -16000 -18200
LSB
AFEOutput MaximumDACCode=0x3FF 16000 18200
CDSGain=1x 1.2 mV
DACLSBStepSize
ReferredtoAFEOutput (32) (LSB)
DNL DifferentialNon-Linearity -0.95 3.25 LSB
INL IntegralNon-Linearity -3.1 2.65 LSB
PGASpecifications
GainResolution 8 Bits
Monotonicity Ensuredbycharacterization
CDSGain=1x 7.18 7.9 8.77 V/V
MaximumGain
CDSGain=1x 17.1 17.9 18.9 dB
CDSGain=1x 0.56 0.7 0.82 V/V
MinimumGain
CDSGain=1x -5 -3 -1.72 dB
Gain(V/V)=(196/(280-PGACode))
PGAFunction
Gain(dB)=20LOG10(196/(280-PGACode))
MinimumPGAGain 3
ChannelMatching %
MaximumPGAGain 12.7
ADCSpecifications
V TopofReference 2.07 V
REFT
V BottomofReference 0.89 V
REFB
V -
REFT DifferentialReferenceVoltage 1.07 1.18 1.29 V
V
REFB
OverrangeOutputCode 65535
UnderrangeOutputCode 0
DigitalOffset“DAC”Specifications
Resolution 7 Bits
DigitalOffsetDACLSBStepSize ReferredtoAFEOutput 16 LSB
MinDACCode=7b0000000 -1024
OffsetAdjustmentRange
MidDACCode=7b1000000 0 LSB
ReferredtoAFEOutput
MaxDACCode=7b1111111 1008
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