20-Stage Pipelined ADC with Radix

46 Pages·2004·0.28 MB·English

20-Stage Pipelined ADC with Radix-Based Calibration

by
Chong Kyu Yun

A THESIS

submitted to

Oregon State University

in partial fulfillment of
the requirements for the
degree of

Master of Science

Presented November 7, 2002
Commencement June 2003
ACKNOWLEDGEMENTS
I would like to thank my advisor, Dr. Un-Ku Moon, for his patience and
valuable guidance throughout my graduate study. His criticism and advice made me
grow not only as an engineer, but as a person. I would also like to thank the members
of my thesis committee for their helpful feedback
Thanks to Gil-Cho Ahn for his insights and helpful comments on the pipelined
ADC as well as a wide range of subjects in the analog field. Thanks to Dong-Young
Chang for helping me start in the beginning of the research. Thanks to my friends
Pavan Hanumolu, Jipeng Li, Anurag Pulincherry and José Silva for their patience and
accessibility whenever I had technical questions.
I would like to thank the members of Korean Student Association of
Computer Science and Electrical and Computer Engineering for their social
contribution to my experience as a graduate student at Oregon State University.
I would like to thank my roommates Chi-Young Lim and Ki-Seok Yoo for
being cool to live under the same roof.
I would like to thank my family for their endless support. I would like to
thank my parents for patiently listening to my thoughts on my future and advising me.
I would like to thank my sister for conversing with me about many different issues of
my life.
Finally, I would like to thank my God for always being there and listening to
my countless prayers in my good times and bad times. I could not have completed
my graduate study without Him.
TABLE OF CONTENTS
Page
1. INTRODUCTION......................................................................................................1
2. PIPELINED ARCHITECTURE.................................................................................3
2.1. General Pipelined ADC..............................................................................3
2.2. 1-bit/stage Pipelined ADC..........................................................................4
2.3. Error Sources in 1-bit/stage Pipelined ADC...............................................7
3. REVIEW OF CALIBRATION TECHNIQUES.........................................................9
3.1. A 15-b 1-Msample/s Digitally Self-Calibrated Pipelined ADC [8]...........9
3.2. A Digitally Self-Calibrated Pipelined Algorithmic ADC [9]...................10
3.3. A Continuously Calibrated 12-b 10-MS/s, 3.3-V A/D Converter [11].....11
3.4. A 12-b Digital-Background-Calibrated Algorithmic ADC [12]...............13
4. RADIX-BASED CALIBRATION TECHNIQUE...................................................16
4.1. Necessity of a Sub-Radix-2 System.........................................................16
4.2. Radix-Based Calibration..........................................................................19
4.2.1. Fundamental Concept...................................................................19
4.2.2. Radix Measurement......................................................................20
5. CIRCUIT IMPLEMENTATION OF A PIPELINED ADC WITH RADIX-BASED
CALIBRATION.......................................................................................................22
5.1. Timing of the Pipelined ADC...................................................................22
5.2. Multiplying Digital-to-Analog Converter................................................24
5.2.1. Operational Amplifier...................................................................26
5.2.2. Common-Mode Feedback............................................................28
5.2.3. Biasing..........................................................................................29
5.2.4. Simulation Results........................................................................30
5.3. Sub-ADC..................................................................................................32
5.4. Latch Block..............................................................................................34
6. SIMULATION RESULTS........................................................................................35
7. CONCLUSION........................................................................................................39
BIBLIOGRAPHY........................................................................................................40
LIST OF FIGURES
Figure Page
2.1. Block diagram of a typical pipelined ADC.............................................................3
2.2. Block diagram of the first stage..............................................................................4
2.3. 1-bit/stage pipelined ADC.......................................................................................4
2.4. Operation of pipelined ADC stages.........................................................................5
2.5. Ideal residue transfer characteristics of a pipeline stage.........................................6
2.6. Ideal MDAC used in a pipelined stage....................................................................7
2.7. Residue transfer characteristics: (a) with capacitor mismatch; (b) with offset
errors........................................................................................................................8
3.1. Digital calibration presented in [8]..........................................................................9
3.2. 1.5 bit/stage pipelined stage used in [9]................................................................11
3.3. Transfer characteristics of a pipeline stage: (a) with adjusted V and (b) after
TH
calibration [11]......................................................................................................12
3.4. Determination of V(n) which produces output (1+ β)V [11]..........................13
REFP
3.5. Determination of V [11]...................................................................................13
THA
3.6. An algorithmic ADC used in [12]..........................................................................14
4.1 MDAC with errors..................................................................................................16
4.2. A radix-2 pipeline stage operation with errors......................................................17
4.3. A sub-radix 2 MDAC............................................................................................18
4.4. Operation of a sub-radix 2 pipeline stages............................................................18
4.5. ADC transfer curves: (a) Ideal; (b) Nonlinear.......................................................20
4.6. Radix measurements in a 20-stage pipelined ADC...............................................20
5.1. Timing diagram of ADC operation........................................................................22
5.2. Schematic of a pipeline stage................................................................................23
5.3. Circuit diagram of MDAC....................................................................................25
5.4. Schematic of the Op Amp.....................................................................................26
5.5. Common-mode feedback circuit...........................................................................29
5.6. Op Amp Bias Circuit.............................................................................................30
LIST OF FIGURES (Continued)
Figure Page
5.7. AC analysis of MDAC..........................................................................................31
5.8. Transient analysis of MDAC.................................................................................31
5.9. Schematic of the comparator.................................................................................32
5.10. Pre-amplifier in the comparator...........................................................................33
5.11. Comparator latch.................................................................................................33
5.12. Latch block..........................................................................................................34
6.1. Radix measurements..............................................................................................35
6.2. FFT plot of MATLAB simulation: (a) before calibration and (b) after
calibration..............................................................................................................36
6.3. FFT plot of the circuit level simulation: (a) before calibration and (b) after
calibration..............................................................................................................37
20-STAGE PIPELINED ADC WITH RADIX-BASED CALIBRATION
1. INTRODUCTION
The continuous effort to improve the performance of analog-to-digital
converters (ADC) has led the development of several precision techniques for ADC’s.
The primary objective of those precision techniques is to alleviate the accuracy
constraints such as capacitor mismatch, charge injection, finite op amp DC gain and
comparator offset. In the early years, the error correcting techniques like the ratio-
independent [1], reference refreshing [2], capacitor error-averaging [3], on-chip
capacitor trimming [4] and analog calibration [5] were applied in the analog domain.
The main drawback of these analog precision techniques is the complexity of circuit
implementation. The digitally controlled self-calibration [6] and digital-domain
calibration [7] techniques were introduced to eliminate the disadvantage of the analog
precision techniques but developed for successive approximation and flash type
ADC’s, respectively.
Due to the simplicity and relative easiness to achieve high resolution and high
speed, the 1-bit/stage pipelined architecture has been used and calibration techniques
[8]-[12] and [14] have been developed for it recently. The digital self-calibration
technique proposed in [8] compensates for errors mentioned above but the overall
transfer characteristics of the ADC are dependent upon the actual residue gains of each
stage. The technique presented in [9] resolves the dependability of inter-stages but
the finite op amp DC gain is not compensated. While the technique introduced in
[11] has an advantage of continuous calibration, it requires an extra stage. The
calibration algorithm presented in [12] overcomes these limitations addressed above
but applies only to a single-stage algorithmic ADC.
The radix-based calibration proposed in [14] extends the technique [12] to a
multi-stage algorithmic or pipelined architecture. To show the concept of radix-based
calibration, a two-stage algorithmic ADC is used in [14]. Because the two-stage
algorithmic ADC has only two different radices, which are repeatedly used for
calibration, this does not show the effect of a true multi-stage ADC in which the radix
2
for each stage differs from each other. The primary objective is to verify the
capability of the radix-based calibration in a multi-stage ADC as which a 1-bit/stage
pipelined ADC is used.
The thesis organization is as follows. Chapter 2 describes the general
pipelined architecture and specifies in the 1-bit/stage pipelined ADC. The sources of
errors in a 1-bit/stage pipelined ADC is also addressed in the chapter. Some of the
calibration techniques mentioned above are revisited with details in Chapter 3.
Chapter 4 presents the radix-calibration techniques as well as the necessity of sub-
radix-2 system. Chapter 5 is devoted to the circuit implementation of the 20-stage
pipelined ADC with radix-based calibration. The simulation results are given in
Chapter 6. Finally, Chapter 7 provides conclusion for this thesis.
3
2. PIPELINED ARCHITECTURE
A brief description of a general pipelined ADC architecture is first presented
in this chapter. A single-bit-per-stage pipelined ADC, for which the radix-based
calibration is used, is next described in details. The error sources and their effects in
a pipelined ADC conclude this chapter.
2.1. General Pipelined ADC
STG 1 STG 2 STG N
Analog in
D D D
K
Digital Delay Logic Digital out

Figure 2.1. Block diagram of a typical pipelined ADC
Figure 2.1 shows a block diagram of a general N-stage pipelined ADC.
Each stage consists of a multiplying digital-to-analog converter (MDAC) and a sub-
ADC. An illustration on one stage is given in Figure 2.2. An external analog signal
is sampled in the first stage. The sampled signal is then quantized by the sub-ADC
yielding a D-bit digital output. The quantized signal is converted back to an analog
signal in MDAC and subtracted from the original input signal, V . The resulting
IN
quantity is multiplied by the amplifier gain 2D to produce the residue voltage, V ,
RES,1
in full reference range for the next stage. V is sampled and processed in the
RES,1
similar manner on the next clock phase. Due to the concurrent stage residue
processes and the successive sampling of the stage inputs, the corresponding digital
outputs of each stage for a sampled input at a specific time are not aligned. In order
to align the digital outputs in phase, an appropriate delay-logic is necessary. The
digital delay logic exists to resolve the issue. The total number of bits is K = N ⋅D.
The digital output of the pipelined ADC is
D = D ⋅2N−1 +D ⋅2N−2 + + D ⋅21 +D . (2.1)
OUT 1 2 L N−1 N
4
V MDAC V
IN RES,1
(x2D)
sub-ADC
D bits

Figure 2.2. Block diagram of the first stage
2.2. 1-bit/stage Pipelined ADC
The prototype architecture is a single-bit-per-stage pipelined ADC. The
advantage of it is simplicity and speed. The low resolution per stage reduces the
requirements for the sub-ADC comparator from those of the higher resolution per
stage architecture. The fewer bits per stage realized, the smaller gain for MDAC
required. As the gain decreases, the bandwidth of the MDAC amplifiers increases
granting higher speed for each stage to resolve their digital outputs. The only
limitation for the sampling rate is the time to generate the bits for one stage. Hence,
higher speed is allowed for an architecture with a fewer number of bits per stage.
STG 1 STG 2 STG 20
V
IN 1 1 1
20 bits
Digital Delay Logic Digital out
V MDAC V
RES,1 RES,2
(x2)
D
sub-ADC OUT
1 bit

Figure 2.3. 1-bit/stage pipelined ADC
5
A 1-bit/stage pipelined ADC with 20 stages is illustrated in Figure 2.3. The
input range is from -V to +V . With the sampled input at the first stage, each
REF REF
stage produces a corresponding single bit at their proper clock cycle. The sub-ADC
threshold is the midpoint between -V and +V . The prototype uses the common-
REF REF
mode voltage for the comparator threshold because the system is unipolar. For the
purpose of simple explanation, a bipolar system is considered. In a bipolar system,
the sub-ADC threshold is zero. The operation of the ADC is shown in Figure 2.4.
Only the first three stages are shown for simplicity. If the input of a stage is greater
than zero, the digital output is one and the input is subtracted by +V and amplified
REF
by the gain of two. If the input of a stage is less than zero, the digital output is zero
and the input is subtracted by -V and amplified by two. Then, the residue transfer
REF
function is as follows:
  V 
2⋅V − REF  if V ≥0, D =1
  IN 2  IN
V =  (2.2)
RES
2⋅V +VREF  if V < 0, D =0
  IN 2  IN
A graphical representation of the residue transfer function is shown in Figure 2.5.
STG 1 STG 2 STG 3
+V +V +V
REF REF REF
 V 
D = 1 2⋅V − REF 
 IN 2 
 V 
D = 0 2⋅V + REF 
 IN 2 
-V -V -V
REF REF REF
Digital Outputs 1 0 1

Figure 2.4. Operation of pipelined ADC stages