18-Bit, 1-MSPS, Pseudo-Bipolar Differential SAR ADC with On-Chip ADC Driver PDF
Preview 18-Bit, 1-MSPS, Pseudo-Bipolar Differential SAR ADC with On-Chip ADC Driver
Not Recommended for New Designs ADS8284 SLAS628A–MARCH2009–REVISEDAPRIL2014 ADS8284 18-BIT, 1-MSPS, Pseudo-Bipolar Differential SAR ADC with On-Chip ADC Driver (OPA) and 4-Channel Differential Multiplexer 1 Features 3 Description • 1.0-MHzSampleRate,ZeroLatencyatFull The ADS8284 is a high-performance analog system- 1 on-chip (SoC) device with an 18-bit, 1-MSPS A/D Speed converter, 4-V internal reference, an on-chip ADC • 18-BitResolution driver (OPA), and a 4-channel differential multiplexer. • SupportsPseudo-BipolarDifferentialInputRange: Thechannelcountofthemultiplexerandauto/manual -4Vto+4Vwith2-V Common-Mode scanmodesofthedeviceareuserselectable. • Built-InFourChannel,DifferentialEnded The ADC driver is designed to leverage the very high Multiplexer;withChannelCountSelectionand noise performance of the differential ADC at optimum Auto/ManualMode power usagelevels. • On-BoardDifferentialADCDriver(OPA) The ADS8284 outputs a buffered reference signal for • BufferedReferenceOutputtoLevelShiftBipolar level shifting of a ±4-V bipolar signal with an external ±4-VInputwithExternalResistanceDivider resistance divider. A V /2 output signal is available ref to set the common-mode of a signal conditioning • Reference/2OutputtoSetCommon-Modefor circuit. The device also includes an 18-/16-/8-bit ExternalSignalConditioner parallelinterface. • 18-/16-/8-BitParallel Interface The ADS8284 is available in a 9 mm x 9 mm, 64-pin • SNR: 98.4dBTypat2-kHzI/P QFN package and is characterized from -40°C to • THD:–119dBTypat2-kHzI/P 85°C. • PowerDissipation:331.25mWat1MSPS IncludingADCDriver DeviceInformation (1) • InternalReference DEVICENAME PACKAGE BODYSIZE • InternalReferenceBuffer ADS8284 QFN(64) 9mmx9mm • 64-PinQFNPackage (1) For all available packages, see the orderable addendum at theendofthedatasheet. 2 Applications • MedicalImaging/CTScanners • AutomatedTestEquipment • High-SpeedDataAcquisitionSystems • High-SpeedClosed-LoopSystems SimplifiedSchematic Analog 5 V 0.1 m F AGND 10 m F Ext Ref Input 0.1 m F Analog Input AN MD N N Micro +VREFI REFAGN +I −I Controller Digital 3 V GPIO CS AD8284 GPIO BYTE 0.1 m F GPIO BUS18/16 BDGND GPIO CONVST RD RD BDGND +VBD AD[7:0] DB[17:10] Data Bus D[17:0] 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA. Not Recommended for New Designs ADS8284 SLAS628A–MARCH2009–REVISEDAPRIL2014 www.ti.com Table of Contents 1 Features.................................................................. 1 6.10 TypicalCharacteristics..........................................19 2 Applications........................................................... 1 7 DeviceDescription............................................... 30 3 Description............................................................. 1 7.1 Overview.................................................................30 4 RevisionHistory..................................................... 2 7.2 FunctionalBlockDiagram.......................................30 7.3 FeatureDescription.................................................31 5 PinConfigurationandFunction........................... 3 7.4 DeviceFunctionalModes........................................32 6 Specifications......................................................... 6 8 ApplicationandImplementation........................ 33 6.1 AbsoluteMaximumRatings .....................................6 8.1 ApplicationInformation............................................33 6.2 HandlingRatings.......................................................6 8.2 TypicalApplications................................................33 6.3 RecommendedOperatingConditions.......................6 9 PowerSupplyRecommendations...................... 36 6.4 ThermalInformation..................................................6 6.5 ElectricalCharacteristics...........................................7 10 DeviceandDocumentationSupport................. 37 6.6 TimingRequirements,5V......................................10 10.1 Trademarks...........................................................37 6.7 TimingRequirements,3V......................................11 10.2 ElectrostaticDischargeCaution............................37 6.8 MultiplexerTimingRequirements...........................11 10.3 Glossary................................................................37 6.9 TimingDiagrams.....................................................12 11 Mechanical,Packaging,andOrderable Information........................................................... 37 4 Revision History ChangesfromOriginal(March2009)toRevisionA Page • ChangedthedatasheettothenewTIstandard ................................................................................................................... 1 • AddedtheDeviceInformationtable....................................................................................................................................... 1 • AddedtheHandlingRatingstable.......................................................................................................................................... 6 • AddedReference/2VoltageRangetotheElectricalCharacteristicstable ........................................................................... 8 • AddedthePowerSupplyRecommendationssection.......................................................................................................... 36 2 SubmitDocumentationFeedback Copyright©2009–2014,TexasInstrumentsIncorporated ProductFolderLinks:ADS8284 Not Recommended for New Designs ADS8284 www.ti.com SLAS628A–MARCH2009–REVISEDAPRIL2014 DeviceComparisonTable TYPE/SPEED 500kHz ~600kHz 750kHz 1MHz 1.25MHz 2MHz 3MHz 4MHz ADS8383 ADS8381 ADS8481 18-BitPseudo-Diff ADS8380(s) ADS8382(s) ADS8284 ADS8484 18-BitPseudo-Bipolar,FullyDiff ADS8482 ADS8327 ADS8370(s) ADS8371 ADS8471 ADS8401 ADS8411 16-BitPseudo-Diff ADS8328 ADS8405 ADS8410(s) ADS8319 ADS8318 ADS8372(s) ADS8472 ADS8402 ADS8412 ADS8422 16-BitPseudo-Bipolar,FullyDiff ADS8254 ADS8406 ADS8413(s) 14-BitPseudo-Diff ADS7890(s) ADS7891 12-BitPseudo-Diff ADS7886 ADS7883 ADS7881 DeviceLinearity MODEL MAXIMUMINTEGRAL MAXIMUMDIFFERENTIAL NOMISSINGCODESAT LINEARITY LINEARITY RESOLUTION (LSB) (LSB) (BIT) ADS8284lB ±2.5 +1.5/–1 18 ADS8284l ±4.5 +1.5/–1 18 5 Pin Configuration and Function QFN PACKAGE (TOPVIEW) F T T E U S F-R MO A ND FO FIN FM FMAND A NV TE CU C V G E E E EVG V S D O Y NB V + A R R R R+A + C R C B 16 1514 13 12 11 10 9 8 7 6 5 4 3 2 1 CH0P 17 64 BUS18_16 CH0M 18 63 +VBD CH1P 19 62 BUSY CH1M 20 61 DB0 PD-RBUF 21 60 DB1 VEE 22 59 DB2 VCC 23 58 DB3 VCC 24 ADS8284 57 DB4 INP 25 56 DB5 AGND 26 55 DB6 INM 27 54 DB7 NC 28 53 DB8 CH2P 29 52 DB9 CH2M 30 51 BGND CH3P 31 50 +VBD CH3M 32 49 DB10 3334 35 36 37 3839 40 4142 434445 46 47 48 O 32 1 KA D A D 7 65 4 3 2 1 AUT CC C XCL+V AGN +V AGN DB1 DB1DB1 DB1 DB1 DB1 DB1 M Copyright©2009–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:ADS8284 Not Recommended for New Designs ADS8284 SLAS628A–MARCH2009–REVISEDAPRIL2014 www.ti.com PinFunctions PIN I/O DESCRIPTION NO NAME MULTIPLEXERINPUTPINS Non-invertinganaloginputfordifferentialmultiplexerchannelnumber0.Deviceperformanceisoptimizedfor50-Ωsource 17 CH0P I impedanceatthisinput. Invertinganaloginputfordifferentialmultiplexerchannelnumber0.Deviceperformanceisoptimizedfor50-Ωsource 18 CH0M I impedanceatthisinput. Non-invertinganaloginputfordifferentialmultiplexerchannelnumber1.Deviceperformanceisoptimizedfor50-Ωsource 19 CH1P I impedanceatthisinput. Invertinganaloginputfordifferentialmultiplexerchannelnumber1.Deviceperformanceisoptimizedfor50-Ωsource 20 CH1M I impedanceatthisinput. Non-invertinganaloginputfordifferentialmultiplexerchannelnumber2.Deviceperformanceisoptimizedfor50-Ωsource 29 CH2P I impedanceatthisinput. Invertinganaloginputfordifferentialmultiplexerchannelnumber2.Deviceperformanceisoptimizedfor50-Ωsource 30 CH2M I impedanceatthisinput. Non-invertinganaloginputfordifferentialmultiplexerchannelnumber3.Deviceperformanceisoptimizedfor50ohmsource 31 CH3P I impedanceatthisinput. Invertinganaloginputfordifferentialmultiplexerchannelnumber3.Deviceperformanceisoptimizedfor50-Ωsource 32 CH3M I impedanceatthisinput. ADCINPUTPINS 25 INP I ADCNoninvertinginput.,connect1-nFcapacitoracrossINPandINM 27 INM I ADCInvertinginput,connect1-nFcapacitoracrossINPandINM REFERENCEINPUT/OUTPUTPINS 8,9 REFM I Referenceground. 10 REFIN I ReferenceInput.Add0.1-μFdecouplingcapacitorbetweenREFINandREFM. 11 REFOUT O ReferenceOutput.Add1-μFcapacitorbetweentheREFOUTpinandREFMpinwheninternalreferenceisused. 14 VCMO O ThispinoutputsREFIN/2andcanbeusedtosetcommon-modevoltageofdifferentialanaloginputs. 15 BUF-REF O Bufferedreferenceoutput.Usefultolevelshiftbipolarsignalsusingexternalresistors. POWERCONTROLPINS 21 PD-RBUF I Highonthispinpowersdownthereferencebuffer(BUF-REF). MULTIPLEXERCONTROLPINS 33 AUTO I Highlevelonthispinselectsautomodeformultiplexerscanning.Lowlevelselectsmanualmodeofmultiplexerscanning Inautomode(AUTO=1)multiplexerchannelselectionisresettoCH0onrisingedgeofMXCLKwhileC3=1.Thepinisdo 34 C3 I notcareinmanualmode. ActsasmultiplexeraddressbitwhenAUTO=0(manualmode).Inautomode(AUTO=1)C2andC1selectthelast 35 C2 I multiplexerchannel(channelcount)intheautoscansequence. ActsasmultiplexeraddressLSBwhenAUTO=0(manualmode).Inautomode(AUTO=1)C2andC1selectthelast 36 C1 I multiplexerchannel(channelcount)intheautoscansequence. MultiplexerchannelisselectedonrisingedgeofMXCLKirrespectiveofwhetheritisautoormanualmode.DeviceBUSY 37 MXCLK I outputcanbeconnectedtoMXCLKsothatdeviceselectsnextchannelattheendofeverysample. ADCDATABUS 8-BITBUS 16-BITBUS 18-BITBUS 42-49, DataBus BYTE=0 BYTE=1 BYTE=1 BYTE=0 BYTE=0 BYTE=0 52-61 BUS18/16=0 BUS18/16=0 BUS18/16=1 BUS18/16=0 BUS18/16=1 BUS18/16=0 42 DB17 O D17(MSB) D9 Allones D17(MSB) Allones D17(MSB) 43 DB16 O D16 D8 Allones D16 Allones D16 44 DB15 O D15 D7 Allones D15 Allones D15 45 DB14 O D14 D6 Allones D14 Allones D14 46 DB13 O D13 D5 Allones D13 Allones D13 47 DB12 O D12 D4 Allones D12 Allones D12 48 DB11 O D11 D3 D1 D11 Allones D11 49 DB10 O D10 D2 D0(LSB) D10 Allones D10 52 DB9 O D9 Allones Allones D9 Allones D9 53 DB8 O D8 Allones Allones D8 Allones D8 54 DB7 O D7 Allones Allones D7 Allones D7 55 DB6 O D6 Allones Allones D6 Allones D6 56 DB5 O D5 Allones Allones D5 Allones D5 4 SubmitDocumentationFeedback Copyright©2009–2014,TexasInstrumentsIncorporated ProductFolderLinks:ADS8284 Not Recommended for New Designs ADS8284 www.ti.com SLAS628A–MARCH2009–REVISEDAPRIL2014 PinFunctions (continued) PIN I/O DESCRIPTION NO NAME 57 DB4 O D4 Allones Allones D4 Allones D4 58 DB3 O D3 Allones Allones D3 D1 D3 59 DB2 O D2 Allones Allones D2 D0(LSB) D2 60 DB1 O D1 Allones Allones D1 Allones D1 61 DB0 O D0(LSB) Allones Allones D0(LSB) Allones D0(LSB) ADCCONTROLPINS 62 BUSY O Statusoutput.Thispinisheldhighwhendeviceisconverting. 64 BUS18_16 I Bussizeselectinput.Usedforselecting18-bitor16-bitwidebustransfer.RefertoADCDATABUSdescriptionabove. 1 BYTE I ByteSelectInput.Usedfor8-bitbusreading.RefertoADCDATABUSdescriptionabove. 2 CONVST I Convertstart.ThisinputisactivelowandcanactindependentoftheCSinput. 3 RD I Synchronizationpulsefortheparalleloutput. 4 CS I Chipselect. DEVICEPOWERSUPPLIES 22 VEE NegativesupplyforOPA(OP1,OP2) 23,24 VCC PositivesupplyforOPA(OP1,OP2,BUF-REF) 5,7, 13,38, +VA Analogpowersupply. 40 6,12, 26,39, AGND Analogground. 41 50,63 +VBD DigitalpowersupplyforADCbus. 51 BGND DigitalgroundforADCbusinterfacedigitalsupply. NOTCONNECTEDPINS 16,28 NC Noconnection. Copyright©2009–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:ADS8284 Not Recommended for New Designs ADS8284 SLAS628A–MARCH2009–REVISEDAPRIL2014 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT CH(i)toAGND(bothPandMinputs) VEE–0.3 VCC+0.3 V VCCtoVEE -0.3 18 V +VAtoAGND –0.3 7 V +VBDtoBDGND –0.3 7 V ADCcontroldigitalinputvoltagetoGND –0.3 (+VBD+0.3) V ADCcontroldigitaloutputtoGND –0.3 (+VBD+0.3) V MultiplexercontroldigitalinputvoltagetoGND –0.3 (+VA+0.3) V PowercontroldigitalinputvoltagetoGND –0.3 (+VCC+0.3) V Operatingtemperaturerange –40 85 °C Junctiontemperature(Tmax) 150 °C J (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 6.2 Handling Ratings MIN MAX UNIT T Storagetemperaturerange –65 150 °C stg Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,all pins(1) –2 2 kV V Electrostaticdischarge (ESD) Chargeddevicemodel(CDM),perJEDECspecification JESD22-C101,allpins(2) –500 500 V (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT AnalogInputatMultiplexerInputs CHxP,CHxM 0 V V REF DigitalSupplyVoltage +VBD 2.7 3.3 5.25 V AnalogSupplyVoltage +VA 4.75 5 5.25 V PositiveSupplyVoltageforOPA VCC 4.75 5 7.5 V NegativeSupplyVoltageforOPA VEE –7.5 –5 –3 V 6.4 Thermal Information RCG THERMALMETRIC(1) UNIT 64PINS R Junction-to-ambientthermalresistance 24.0 θJA R Junction-to-case(top)thermalresistance 7.8 θJC(top) R Junction-to-boardthermalresistance 3.2 θJB °C/W ψ Junction-to-topcharacterizationparameter 0.1 JT ψ Junction-to-boardcharacterizationparameter 3.2 JB R Junction-to-case(bottom)thermalresistance n/a θJC(bottom) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. 6 SubmitDocumentationFeedback Copyright©2009–2014,TexasInstrumentsIncorporated ProductFolderLinks:ADS8284 Not Recommended for New Designs ADS8284 www.ti.com SLAS628A–MARCH2009–REVISEDAPRIL2014 6.5 Electrical Characteristics T =–40°Cto85°C,VCC=5V,VEE=–5V,+VA=5V,+VBD=5Vor3.3V,V =4V,f =1MSPS(unless A ref SAMPLE otherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT ANALOGINPUT Full-scaleinputvoltageatmultiplexerinput(1) CH(i)P–CH(i)M –Vref Vref V Absoluteinputrangeatmultiplexerinput CH(i) –0.2 Vref+0.2 V Inputcommon-modevoltage [CH(i)P+CH(i)M]/2 (Vref)/2 (Vref)/2 (Vref)/2 V –0.2 +0.2 SYSTEMPERFORMANCE Resolution 18 Bits ADS8284IB 18 Nomissingcodes Bits ADS8284I 18 ADS8284IB –2.5 ±1.25 2.5 Integrallinearity(2) LSB(3) ADS8284I –4.5 ±1.5 4.5 ADS8284IB –1 ±0.6 1.5 Differentiallinearity At18-bitlevel LSB(3) ADS8284I –1 ±0.6 1.5 ADS8284IB –0.5 ±0.05 0.5 Offseterror mV ADS8284I –0.5 ±0.05 0.5 ADS8284IB –0.1 ±0.025 0.1 Gainerror(4) Externalreference %FS ADS8284I –0.1 ±0.025 0.1 DCpowersupplyrejectionratio At3FFF0Houtputcode.For+VAorVCC,VEE 80 dB variationof0.5Vindividually SAMPLINGDYNAMICS +VBD=5V 625 650 ns Conversiontime +VDB=3V 625 650 ns +VBD=5V 320 350 ns Acquisitiontime +VDB=3V 320 350 Maximumthroughputrate 1.0 MHz Aperturedelay 4 ns Aperturejitter 5 ps ForADConly 150 ns Settlingtimeto0.5LSB ForOPA(OP1,OP2)+mux 700 Overvoltagerecovery ForADConly 150 ns DYNAMICCHARACTERISTICS ADS8284I –119 VIN=4Vppat2kHz dB ADS8284IB –119 Totalharmonicdistortion ADS8284I –105 (THD)(5) ADS8284IB VIN=4Vppat10kHz –105 dB ADS8284I VIN=4Vppat100kHz, –100 dB ADS8284IB LoPWR=0 –100 ADS8284I 98.4 VIN=4Vppat2kHz dB ADS8284IB 97.5 98.4 ADS8284I 98 Signal-to-noiseratio(SNR) VIN=4Vppat10kHz dB ADS8284IB 98 ADS8284I VIN=4Vppat100kHz, 95 dB ADS8284IB LoPWR=0 97 (1) Idealinputspan,doesnotincludegainoroffseterror. (2) ThisisendpointINL,notbestfit. (3) LSBmeansleastsignificantbit. (4) Calculatedonthefirstnineharmonicsoftheinputfrequency. (5) Measuredrelativetoacutalmeasuredreference. Copyright©2009–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:ADS8284 Not Recommended for New Designs ADS8284 SLAS628A–MARCH2009–REVISEDAPRIL2014 www.ti.com Electrical Characteristics (continued) T =–40°Cto85°C,VCC=5V,VEE=–5V,+VA=5V,+VBD=5Vor3.3V,V =4V,f =1MSPS(unless A ref SAMPLE otherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT ADS8284I 98.3 VIN=4Vppat2kHz dB ADS8284IB 98.3 Signal-to-noise+distortion ADS8284I 97.2 (SINAD) ADS8284IB VIN=4Vppat10kHz 97.2 dB ADS8284I VIN=4Vppat100kHz, 93.8 dB ADS8284IB LoPWR=0 95.23 ADS8284I 121 VIN=4Vppat2kHz dB ADS8284IB 121 Spuriousfreedynamic ADS8284I 106 range(SFDR) ADS8284IB VIN=4Vppat10kHz 106 dB ADS8284I VIN=4Vppat100kHz, 101 dB ADS8284IB LoPWR=0 101 –3dBsmallsignalbandwidth 8 MHz VOLTAGEREFERENCEINPUT(REFIN) ReferencevoltageatREFIN,Vref 3.0 4.096 +VA–0.8 V Referenceinputcurrent(6) 1 1 μA INTERNALREFERENCEOUTPUT(REFOUT) Internalreferencestart-uptime From95%(+VA),with1-μFstoragecapacitor 120 ms Referencevoltagerange,Vref 4.081 4.096 4.111 V Sourcecurrent Staticload 10 μA Lineregulation +VA=4.75Vto5.25V 60 μV Drift IO=0 ±6 PPM/°C BUFFEREDREFERENCEOUTPUT(BUF-REF) Outputcurrent REFIN=4V,at85°C 70 mA REFERENCE/2OUTPUT(VCMO) Reference/2VoltageRange AtNoLoadonVCMO 1.938 2.048 2.158 V Outputcurrent REFIN=4V,at+85°C 50 μA ANALOGMULTIPLEXER Numberofchannels 4 Channeltochannelcrosstalk 100kHzi/p –95 dB Autosequencerwithselectionofchannelcountor Channelselection manualselectionthroughcontrollines DIGITALINPUT-OUTPUT ADCCONTROLPINS LogicFamily-CMOS VIH IIH=5μA +VBD–1 +VBD+0.3 V VIL IIL=5μA 0.3 0.8 V Logiclevel VOH IOH=2TTLloads +VBD–0.6 +VBD V VOL IOL=2TTLloads 0 0.4 V MULTIPLEXERCONTROLPINS LogicFamily-CMOS IIH IIH=5μA 2.3 +VA+0.3 V Logiclevel IIL IIL=5μA –0.3 0.8 V POWERCONTROLPINS LogicFamily-CMOS VIH IIH=5μA 2.3 +VA+0.3 V Logiclevel VIL IIL=5μA –0.3 0.8 V (6) Canvary±20% 8 SubmitDocumentationFeedback Copyright©2009–2014,TexasInstrumentsIncorporated ProductFolderLinks:ADS8284 Not Recommended for New Designs ADS8284 www.ti.com SLAS628A–MARCH2009–REVISEDAPRIL2014 Electrical Characteristics (continued) T =–40°Cto85°C,VCC=5V,VEE=–5V,+VA=5V,+VBD=5Vor3.3V,V =4V,f =1MSPS(unless A ref SAMPLE otherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT POWERSUPPLYREQUIREMENTS +VBD 2.7 3.3 5.25 V +VA 4.75 5 5.25 V Powersupplyvoltage VCC 4.75 5 7.5 V VEE –7.5 –5 –3 V ADCdriverpositivesupply(VCC)current(forOP1and VCC=+5,VEE=-5V,CH0-CH3pandminputs 11.65 mA OP2together) shortedtoeachotherandconnectedto2V ADCdrivernegativesupply(VEE)current(forOP1and VCC=+5V,CH0-CH3pandminputsshortedto 9.6 mA OP1together) eachotherandconnectedto2V +VAsupplycurrent,1-MHzsamplerate 45 50 mA Referencebuffer(BUF-REF)supplycurrent(VCCto VCC=+5,PD-RBUF=0,Quiescentcurrent 8 mA GND) VCC=5,PD-RBUF=1(7) 10 μA TEMPERATURERANGE Operatingfree-air –40 85 °C (7) PD-RBUF=1powersdownthereferencebuffer(BUF-REF),notethatitdoesnot3-statetheBUF-REFoutput. Copyright©2009–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:ADS8284 Not Recommended for New Designs ADS8284 SLAS628A–MARCH2009–REVISEDAPRIL2014 www.ti.com 6.6 Timing Requirements, 5 V Allspecificationstypicalat–40°Cto85°C,+VA=+VBD=5V (1) (2) (3) PARAMETER MIN TYP MAX UNIT t Conversiontime 650 ns (CONV) t Acquisitiontime 320 ns (ACQ) t Samplecapacitorholdtime 25 ns (HOLD) t CONVSTlowtoBUSYhigh 40 ns pd1 t Propagationdelaytime,endofconversiontoBUSYlow 15 ns pd2 t Propagationdelaytime,startofconvertstatetorisingedgeofBUSY 15 ns pd3 t Pulseduration,CONVSTlow 40 ns w1 t Setuptime,CSlowtoCONVSTlow 20 ns su1 t Pulseduration,CONVSThigh 20 ns w2 CONVSTfallingedgejitter 10 ps t Pulseduration,BUSYsignallow t min ns w3 (ACQ) t Pulseduration,BUSYsignalhigh 650 ns w4 t Holdtime,firstdatabustransition(RDlow,orCSlowforreadcycle,orBYTEor h1 40 ns BUS18/16inputchanges)afterCONVSTlow t Delaytime,CSlowtoRDlow 0 ns d1 t Setuptime,RDhightoCShigh 0 ns su2 t Pulseduration,RDlow 50 ns w5 t Enabletime,RDlow(orCSlowforreadcycle)todatavalid 20 ns en t Delaytime,dataholdfromRDhigh 5 ns d2 t Delaytime,BUS18/16orBYTErisingedgeorfallingedgetodatavalid 10 20 ns d3 t Pulseduration,RDhigh 20 ns w6 t Pulseduration,CShigh 20 ns w7 t Holdtime,lastRD(orCSforreadcycle)risingedgetoCONVSTfallingedge 50 ns h2 t Propagationdelaytime,BUSYfallingedgetonextRD(orCSforreadcycle)falling pd4 0 ns edge t Delaytime,BYTEedgetoBUS18/16edgeskew 0 ns d4 t Setuptime,BYTEorBUS18/16transitiontoRDfallingedge 10 ns su3 t Holdtime,BYTEorBUS18/16transitiontoRDfallingedge 10 ns h3 t Disabletime,RDhigh(CShighforreadcycle)to3-stateddatabus 20 ns dis t Delaytime,BUSYlowtoMSBdatavaliddelay 0 ns d5 t Delaytime,CSrisingedgetoBUSYfallingedge 50 ns d6 t Delaytime,BUSYfallingedgetoCSrisingedge 50 ns d7 t BYTEtransitionsetuptime,fromBYTEtransitiontonextBYTEtransition,orBUS18/16 su5 50 ns transitionsetuptime,fromBUS18/16tonextBUS18/16. t SetuptimefromthefallingedgeofCONVST(usedtostartthevalidconversion)tothe su(ABORT) nextfallingedgeofCONVST(whenCS=0andCONVSTareusedtoabort)ortothe 60 550 ns nextfallingedgeofCS(whenCSisusedtoabort). (1) Allinputsignalsarespecifiedwitht =t =5ns(10%to90%of+VBD)andtimedfromavoltagelevelof(V +V )/2. r f IL IH (2) Seetimingdiagrams. (3) Alltimingaremeasuredwith20pFequivalentloadsonalldatabitsandBUSYpins. 10 SubmitDocumentationFeedback Copyright©2009–2014,TexasInstrumentsIncorporated ProductFolderLinks:ADS8284
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