16-Bit, 2-MSPS, LVDS Serial Interface, SAR ADC.

40 Pages·2014·0.98 MB·English

ADS8410
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16-BIT, 2-MSPS, LVDS SERIAL INTERFACE,
SAR ANALOG-TO-DIGITAL CONVERTER
CheckforSamples:ADS8410
FEATURES APPLICATIONS
1
• 2-MHzSampleRate • Medical Instrumentation
• 16-BitResolution • HIgh-SpeedDataAcquisitonSystems
• SNR87.5dBat10kHzI/P • High-SpeedClose-LoopSystems
• THD–98dBat10kHzI/P • Communication
• ±1LSBTyp, ±2.5LSBINLMax
DESCRIPTION
• +0.8/–0.5LSBTyp,+1.5/–1LSBDNL Max
The ADS8410 is a 16-bit, 2-MSPS, analog-to-digital
• UnipolarDifferentialInputRange:0V
(A/D) converter with 4-V internal reference. The
to4V
device includes a capacitor based SAR A/D converter
• InternalReference withinherentsampleandhold.
• InternalReferenceBuffer
The ADS8410 also includes a 200-Mbps, LVDS,
• 200-MbpsLVDS SerialInterface serial interface. This interface is designed to support
daisy chaining or cascading of multiple devices. A
• Optional200-MHzInternalInterfaceClock
selectable 16-/8-bit data frame mode enables the use
• 16-/8-BitDataFrame
of a single shift register chip (SN65LVDS152) for
• ZeroLatencyatFullSpeed convertingthedatatoparallelformat.
• PowerDissipation:290mWat2MSPS
The ADS8410 unipolar single-ended input range
• NapMode(125mWPowerDissipation) supportsadifferentialinput swingof0Vto+V .
ref
• PowerDown(5μW) The nap feature provides substantial power saving
• 48-PinQFNPackage whenusedatlowerconversionrates.
TheADS8410isavailableina48-pinQFNpackage.
Table1.High-SpeedSARConverter Family
Type/Speed 500kHz ~600kHz 750kHZ 1MHz 1.25MHz 2MHz 3MHz 4MHz
ADS8383 ADS8381
18-BitPseudo-Diff
ADS8380(S)
18-BitPseudo-Bipolar,FullyDiff ADS8382(S)
ADS8411
16-BitPseudo-Diff ADS8370(S) ADS8371 ADS8401/05 ADS8410
(S-LVDS)
ADS8412
16-BitPseudo-Bipolar,FullyDiff ADS8372(S) ADS8402/06 ADS8413
(S-LVDS)
14-BitPseudo-Diff ADS7890(S) ADS7891
12-BitPseudo-Diff ADS7881
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof
TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2005–2013,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
ADS8410
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+ VA AGND + VBD BDGND
Core Supply I/O Supply
SAR
CSTART
LVDS I/O SYNC_O, CLK_O, SDO
SYNC_I, CLK_I, SDI
+ IN +
CDAC
− IN −
CONVST
Comparator
BUS BUSY
CMOS I/O RD
REFIN
Conversion BUSY
Clock and CS
Control Logic
LAT_Y/N
4 V Internal Mode
BYTE,
REFOUT Reference Selection
MODE_C/D,
CLK_I/E, PD, NAP
ORDERINGINFORMATION(1)
MAXIMUM MAXIMUM NOMISSING
TRANSPORT
INTEGRAL DIFFERENTIAL CODESAT PACKAGE PACKAGE TEMPERATURE ORDERING
MODEL MEDIA
LINEARITY LINEARITY RESOLUTION TYPE DESIGNATOR RANGE INFORMATION
QUANTITY
(LSB) (LSB) (BIT)
48pin –40°C ADS8410IBRGZT 250
ADS8410lB ±2.5 1.5/–1 16 RGZ
QFN to85°C ADS8410IBRGZR 2000
48pin –40°C ADS8410IRGZT 250
ADS8410l ±4 3/–1 16 RGZ
QFN to85°C ADS8410IRGZR 2000
(1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI
websiteatwww.ti.com.
ABSOLUTE MAXIMUM RATINGS
overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)
UNIT
+INtoAGND –0.3Vto+VA+0.3V
-INtoAGND –0.3Vto+0.3V
+VAtoAGND –0.3to7V
+VBDtoBDGND –0.3to7V
DigitalinputvoltagetoGND –0.3Vto(+VBD+0.3V)
DigitaloutputtoGND –0.3Vto(+VBD+0.3V)
Operatingtemperaturerange –40°Cto85°C
Storagetemperaturerange –65°Cto150°C
Junctiontemperature(Tmax) 150°C
J
Powerdissipation (T Max–T )/θ
J A JA
QFNpackage
θ Thermalimpedance 86°C/W
JA
Vaporphase(60sec) 215°C
Leadtemperature,soldering
Infrared(15sec) 220°C
(1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings
only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating
conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
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SPECIFICATIONS
T =–40°Cto85°C,+VA=5V,+VBD=5Vor3.3V,V =4.096V,f =2MHz(unlessotherwisenoted)
A ref sample
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
ANALOGINPUT
Full-scaleinputvoltagespan(1) +IN–(–IN) 0 Vref V
+IN –0.2 Vref+0.2
Absoluteinputvoltagerange V
–IN –0.2 +0.2
Ci Inputcapacitance 25 pF
Inputleakagecurrent 500 pA
SYSTEMPERFORMANCE
Resolution 16 Bits
ADS8410IB 16
Nomissingcodes Bits
ADS8410I 16
ADS8410IB –2.5 ±1 2.5
INL Integrallinearity(2) LSB(3)
ADS8410I –4.0 ±2.5 4.0
ADS8410IB –1 0.8/–0.5 1.5
DNL Differentiallinearity LSB(3)
ADS8410I –1.0 1.5/–0.8 3
ADS8410IB –0.75 ±0.1 0.75
EO Offseterror Externalreference mV
ADS8410I –1.5 ±0.75 1.5
ADS8410IB –0.05 ±0.01 0.05
EG Gainerror(4) Externalreference %ofFS
ADS8410I –0.15 ±0.05 0.15
Withcommonmodeinputsignal=200
CMMR Common-moderejectionratio 60 dB
mVp-pat1MHz
PSRR Powersupplyrejectionratio AtFFF0Houtputcode 80 dB
SAMPLINGDYNAMICS
+VBD=5V 360 391
Conversiontime ns
+VBD=3V 391
+VBD=5V 100
Acquisitiontime ns
+VBD=3V 100
Maximumthroughputratewithorwithoutlatency 2.0 MHz
Aperturedelay 20 ns
Aperturejitter 10 psec
Stepresponse 50 ns
Overvoltagerecovery 50 ns
DYNAMICCHARACTERISTICS
THD Totalharmonicdistortion(5) VIN0.5dBbelowFSat10kHz –98 dB
VIN0.5dBbelowFSat100kHz –92.5
VIN0.5dBbelowFSat10kHz 87.5
SNR Signal-to-noiseratio dB
VIN0.5dBbelowFSat100kHz 86
VIN0.5dBbelowFSat10kHz 87
SINAD Signal-to-noiseanddistortion dB
VIN0.5dBbelowFSat100kHz 85
VIN0.5dBbelowFSat10kHz –101
SFDR Spuriousfreedynamicrange dB
VIN0.5dBbelowFSat100kHz –93
–3dBSmallsignalbandwidth 37.5 MHz
EXTERNALREFERENCEINPUT
Inputvoltagerange,VREF 3.9 4.096 4.2 V
Resistance(6) Tointernalreferencevoltage 500 kΩ
INTERNALREFERENCEOUTPUT
(1) Idealinputspan;doesnotincludegainoroffseterror.
(2) ThisisendpointINL,notbestfit.
(3) Leastsignificantbit
(4) Measuredrelativetoactualmeasuredreference.
(5) Calculatedonthefirstnineharmonicsoftheinputfrequency.
(6) Canvary±20%
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SPECIFICATIONS (continued)
T =–40°Cto85°C,+VA=5V,+VBD=5Vor3.3V,V =4.096V,f =2MHz(unlessotherwisenoted)
A ref sample
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
From95%(+VA),with1-μFstorage 25
Start-uptime ms
capacitoronREFOUTtoAGND
Referencevoltagerange,Vref Atroomtemperature 4.080 4.096 4.112 V
Sourcecurrent Staticload 10 μA
Lineregulation +VA=4.75Vto5.25V 0.6 mV
Drift IOUT=0V 36 PPM/°C
POWERSUPPLYREQUIREMENTS
+VBD 2.7 3.3 5.25
Powersupplyvoltage V
+VA 4.75 5 5.25
Supplycurrent,2-MHzsamplerate +VA 58 64 mA
Powerdissipation,2-MHzsamplerate +VA=5V 290 320 mW
NAPMODE
Supplycurrent +VA 25 mA
POWERDOWN
Supplycurrent +VA 1 2.5 μA
Powerdowntime 10 μs
With1-μFstoragecapacitoron
Poweruptime 25 ms
REFOUTtoAGND
Invalidconversionsafterpoweruporreset 3 Numbers
TEMPERATURERANGE
Operatingfreeair –40 85 °C
LOGICFAMILYCMOS
VIH High-levelinputvoltage IIH=5μA +VBD–1 +VBD+0.3 V
VIL Low-levelinputvoltage IIL=5μA –0.3 0.8 V
VOH High-leveloutputvoltage IOH=2TTLloads +VBD–0.6 +VBD V
VOL Low-leveloutputvoltage IOL=2TTLloads 0 0.4 V
LOGICFAMILYLVDS(7)
DRIVER
Steady-statedifferentialoutputvoltage
|VOD(SS)| magnitude 247 340 454
RL=100Ω,SeeFigure52,Figure53 mV
Changeinsteady-statedifferentialoutputvoltage
∆|VOD(SS)| magnitudebetweenlogicstates -50 50
VOC(SS) Steady-statecommon-modeoutputvoltage 1.125 1.2 1.375 V
Changeinsteady-statecommon-modeoutput
∆|VOC(SS)| voltagebetweenlogicstates SeeFigure54 –50 50
mV
Peaktopeakchangeincommon-modeoutput
VOC(pp) voltage 50 150
VOYorVOZ=0V 3 10
IOS Shortcircuitoutputcurrent mA
VOD=0V 3 10
IOZ Highimpedanceoutputcurrent VO=0Vor+VBD –5 5 μA
(7) Allminmaxvaluesensuredbydesign.
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SPECIFICATIONS (continued)
T =–40°Cto85°C,+VA=5V,+VBD=5Vor3.3V,V =4.096V,f =2MHz(unlessotherwisenoted)
A ref sample
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
RECEIVER
VITH+ Positivegoingdifferentialvoltagethreshold 50
mV
VITH- Negativegoingdifferentialvoltagethreshold –50
VIC Commonmodeinputvoltage 0.2 1.2 2.2 V
CI Inputcapacitance 5 pF
TIMING REQUIREMENTS
T =–40°Cto85°C,+VA=5V,+VBD=5Vor3.3V(unlessotherwisenoted)
A
PARAMETER MIN TYP MAX UNIT REF
SAMPLINGANDCONVERSIONRELATED
Figure1,
tacq Acquisitiontime 100 ns Figure2
Figure1,
tcnv Conversiontime 391 ns Figure2
tw1 Pulseduration,CONVSThigh 100 ns Figure1
Figure1,
tw2 Pulseduration,CONVSTlow 40 ns Figure2
td1 Delaytime,CONVSTrisingedgetosamplestart 5 ns Figure1
Figure1,
td2 Delaytime,CONVSTfallingedgetoconversionstart 5 ns Figure2
+VBD=3.3V 14 Figure1,
td3 Delaytime,CONVSTfallingedgetobusyhigh ns Figure2
+VBD=5V 13
+VBD=3.3V 8 Figure1,
td4 Delaytime,conversionendtobusylow ns Figure2
+VBD=5V 7
Figure1,
tw3 Pulseduration,CSTARThigh 100 ns Table3
Figure1,
tw4 Pulseduration,CSTARTlow 45 ns Figure2,
Table3
Figure1,
td5 Delaytime,CSTARTrisingedgetosamplestart 7.5 ns Table3
Figure1,
td6 Delaytime,CSTARTfallingedgetoconversionstart 7.5 ns Figure2,
Table3
+VBD=3.3V 16.5 Figure1,
td7 Delaytime,CSTARTfallingedgetobusyhigh ns Figure2,
+VBD=5V 15.5 Table3
I/ORELATED
td8 Delaytime,RDfallingedgewhileCSlowtoBUS_BUSYhigh 16 ns Figure5
Delaytime,RDfallingedgewhileCSlowtoSYNC_OandSDOoutof +VBD=3.3V 29
td9 3-statecondition(fordevicewithLAT_Y/Npulledlow) +VBD=5V 28 ns Figure5
td10 Delaytime,pre_conversionend(pointA)toSYNC_OandSDOoutof3-statecondition 22 ns Figure6
+VBD=3.3V 8
td11 Delaytime,pre_conversionend(pointA)toBUS_BUSYhigh ns Figure6
+VBD=5V 7
td12 Delaytime,conversionphaseendtoSYNC_Ohigh 6 9+tCLK ns Figure6
+VBD=3.3V 5.5+4*tCLK 8.5+5*tCLK
td13 Delaytime,RDfallingedgewhileCSlowtoSYNC_Ohigh ns Figure5
+VBD=5V 5+4*tCLK 8+5*tCLK
tw5 Pulseduration,RDlowfordeviceinnolatencymode 5 ns Figure11
+VBD=3.3V 1.4 Figure5,
td14 Delaytime,CLK_Orisingedgetodatavalid +VBD=5V 1.3 ns Figure6
Delaytime,BUS_BUSYlowtoSYNC_Ohighindaisychainmode +VBD=3.3V 4*tCLK–6.5 4*tCLK–3 Figure7,
td15 indicatingreceivingdevicetooutputdata +VBD=5V 4*tCLK–6 4*tCLK–2.5 ns Figure12
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TIMING REQUIREMENTS (continued)
T =–40°Cto85°C,+VA=5V,+VBD=5Vor3.3V(unlessotherwisenoted)
A
PARAMETER MIN TYP MAX UNIT REF
Figure7,
Figure8,
td16 Delaytime,CLK_OtoSDOandSYNC_O3-state 4 ns Figure12,
Figure15
tpd1 Propagationdelaytime,SYNC_ItoSYNC_Oindaisychainmode 11+0.5*tCLK ns Figure12
td17 Delaytime,SYNC_OandSDO3-statetoBUS_BUSYlowincascademode 0 2 ns Figure8
Delaytime,RDrisingedgetoBUS_BUSYhighfordevicewith +VBD=3.3V 8 Figure11,
td18 LAT_Y/N=1 +VBD=5V 7 ns Figure14
Delaytime,pointAindicatingclearforbus3-statereleasetoBUSY +VBD=3.3V 40.5
td19 fallingedge +VBD=5V 40 ns Figure6
tr Risetime,differentialLVDSoutputsignal 950 ps Figure53
tf Falltime,differentialLVDSoutputsignal 950 ps Figure53
CLKfrequency(serialdatarate) 190 210 MHz
Figure22,
td20 Delaytime,fromPDfallingedgetoSDO3-state 10 ns Figure23
Figure22,
td21 Delaytime,fromPDfallingedgetodevicepowerdown 10 μs Figure23
Figure22,
td22 Delaytime,fromPDrisingedgetodevicepowerup 25 ms Figure23
ts1 Settlingtime,internalreferenceafterfirstthreeconversions 4 ms Figure22
td23 Delaytime,CONVSTfallingedgetostartofrestrictedzoneforstartofdatareadcycle 335 ns Figure9
td24 Delaytime,CONVSTfallingedgetoendofrestrictedzoneforstartofdatareadcycle 406 ns Figure9
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DEVICE INFORMATION
RGZPACKAGE
(TOPVIEW)
D
REFM REFM +VA AGND LAT_Y/N CLK_I/E MODE_C/ NAP PD BYTE CONVST CS
12 11 10 9 8 7 6 5 4 3 2 1
REFIN 13 48 BUS_BUSY
REFOUT 14 47 RD
NC 15 46 BUSY
+VA 16 45 BDGND
AGND 17 44 +VBD
+IN 18 43 SYNC_O +
−IN 19 42 SYNC_O −
AGND 20 41 SDO +
+VA 21 40 SDO −
+VA 22 39 CLK_O +
AGND 23 38 CLK_O −
+VA
AGND 24 37
25 26 27 28 29 30 31 32 33 34 35 36
D A D + − + − + − + − D
AGN +V AGN START START YNC_I YNC_I +) SDI −) SDI CLK_I CLK_I AGN
C C S S 2 2
+) −) (M (M
1 1
M M
( (
NC − No internal connection
TERMINALFUNCTIONS
TERMINAL
I/O DESCRIPTION
NO. NAME
ANALOGPINS
11,12 REFM I Referenceground.Connecttoanaloggroundplane.
Reference(positive)input.DecouplewithREFMpinusing0.1-μFbypasscapacitorand1-μFstorage
13 REFIN I
capacitor.
Internalreferenceoutput.ShorttoREFINpinwhentheinternalreferenceisused.Donotconnectto
14 REFOUT O theREFINpinwhenanexternalreferenceisused.AlwaysdecouplewithAGNDusinga0.1-μF
bypasscapacitor.
18 +IN I Noninvertinganaloginputchannel
19 –IN I Invertinganaloginputchannel(supports±0.2Vi/prange)
LVDSI/OPINS(1)
Devicesampleandconvertcontrolinput.Deviceenterssamplephasewiththerisingedgeof
28, CSTART+
I CSTARTandtheconversionphasestartswiththefallingedgeofCSTART(providedotherconditions
29 CSTART–
aresatisfied).SetCSTART=0whentheCONVSTinputisused.
(1) AllLVDSinputsandoutputsaredifferentialwithsignal+andsignal–lines.Wheneveronlythe'signal'ismentioneditreferstothe
signal+lineandthesignal–lineisthecompliment.ForexampleCLK_OreferstoCLK_O+andCLK_Oisthecompliment.
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TERMINALFUNCTIONS(continued)
TERMINAL
I/O DESCRIPTION
NO. NAME
I
SYNC_I+ ConnecttopreviousdeviceSYNC_Owithsamepolarity,whilethedeviceisselectedtooperatein
Dasiy
SYNC_I– daisychainmode.
30, Chain
31 Mode1(validincascademodeonly).CLK_OisavailablewhileM1=1(LVDS)orM1+ispulledupto
M1+ I
+VBDandM1–isgrounded(AGND).CLK_Oo/pgoesto3-statewhenM1=0(LVDS)orM1+is
M1– Cascade
grounded(AGND)andM1–ispulledupto+VBD.Donotallowthesepinstofloat.
I
SDI+ Serialdatainput.ConnecttopreviousdeviceSDOwithsamepolarity,whilethedeviceisselectedto
Daisy
SDI– operateindaisychainmode.
Chain
32,
33 Mode2(validincascademodeonly).DoublesLVDSo/pcurrentwhileM2=1(LVDS)orM2+is
M2+ I pulledupto+VBDandM2–isgrounded(AGND).LVDSo/pcurrentisnormal(3.4mAtyp)whenM2
M2– Cascade =0(LVDS)orM2+isgrounded(AGND)andM2–ispulledupto+VBD.Donotallowthesepinsto
float.
34, CLK_I+
I Serialexternalclockinput.SetCLK_I/E(pin7)=0toselectanexternalclocksource.
35 CLK_I–
38, CLK_O– Serialclockout.DataislatchedoutontherisingedgeofCLK_Oandcanbecapturedonthenext
O
39 CLK_O+ fallingedge.
40, SDO–
O Serialdataout.DataislatchedoutontherisingedgeofCLK_OwithMSBfirstformat.
41 SDO+
42, SYNC_O– O Synchronizesthedataframe. (2)
43 SYNC_O+
CMOSI/OPINS
1 CS I Chipselect,activelowsignal.AlloftheLVDSo/pexceptCLK_Oare3-stateifthispinishigh.
CMOSequivalentofCSTARTinput.SofunctionalityisthesameastheCSTARTinput.SetCONVST
2 CONVST I
=0whentheCSTARTinputisused.
Controlsthedataframe(3)duration.Theframedurationis16CLKsifBYTE=0or8CLKsifBYTE=
3 BYTE I
1.
4 PD I Activelowinput,actsasdevicepowerdown.
Selectsnapmodewhilehigh.Deviceentersthenapstateatconversionendandremainssountilthe
5 NAP I
nextacquisitionphasebegins.
6 MODE_C/D I Selectscascade(MODE_C/D=1)ordaisychainmode(MODE_C/D=0).
SelectsthesourceoftheI/Oclock.
7 CLK_I/E I CLK_I/E=1selectsinternallygeneratedclockwith200-MHztypfrequency.
CLK_I/E=0selectsCLK_IastheI/Oclock.
Controlsthedatareadwithlatency(LAT_Y/N=1)orwithoutlatency((LAT_Y/N=0).Itisessentialto
8 LAT_Y/N I
setLAT_Y/N=0forthefirstdeviceindaisychainorcascade.
46 BUSY O Activehighsignal,indicatesaconversionisinprogress.
Datareadrequesttothedevice,alsoactsasahandshakesignalfordaisychainandcascade
47 RD I
operation.
Statusoutput.Indicatesthatthebusisbeingusedbythedevice.ConnecttoRDofthenextdevice
48 BUS_BUSY O
fordaisychainorcascadeoperation.
POWERSUPPLYPINS
10,16,
21,22, +VA – AnalogpowersupplyandLVDSinputbufferpowersupply.
26,37
9,17,20,
23,24,
AGND – Analoggroundpins.Shorttotheanaloggroundplanebelowthedevice.
25,27,
36
44 +VBD – DigitalpowersupplyforallCMOSdigitalinputsandCMOSLVDSoutputs.
45 BDGND – Digitalgroundforalldigitalinputsandoutputs.Shorttotheanaloggroundplanebelowthedevice.
(2) ThedurationfromthefirstrisingedgeofSYNC_OtothesecondrisingedgeofSYNC_Oisonedataframe.Thedataframedurationis
16CLKsifBYTE=0or8CLKsifBYTE=1.
(3) ThedurationfromthefirstrisingedgeofSYNC_OtothesecondrisingedgeofSYNC_Oisonedataframe.Thedataframedurationis
16CLKsifBYTE=0or8CLKsifBYTE=1.
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TERMINALFUNCTIONS(continued)
TERMINAL
I/O DESCRIPTION
NO. NAME
NOTCONNECTEDPINS
15 NC – Noconnectionpins
Table2.DeviceConfigurationforVariousModesofOperation
DEVICEPINSANDRECOMMENDEDLOGICLEVELS COMMENTS REFERENCEFIGURES
FOR
OPERATIONMODE SAMPLING FORDATA
MODE_C/D CLK_I/E LAT_Y/N M1+ M1– M2+ M2–
AND READ
CONVERSION
+VBD AGND AGND +VBD SeeFigures3,4
1 1or0 0 Recommendedconfiguration 1or2 and5,6,8for
orM1=1LVDS orM2=0LVDS moredetails
Singledevice
SetSYNC_IandSDItologic0 SeeFigures3,4
0 1or0 0 Seecomments Seecomments or+terminaltoAGNDand–ve 1or2 and5,6,7for
terminalto+VBD moredetails
SetSYNC_IandSDItologic0
Multiple 1stDevice 0 1or0 0 Seecomments Seecomments or+terminaltoAGNDand–ve 1or2 SeeFigures
devices terminalto+VBD 3,4,11and6,12
indaisy
chain 2ndTolast 0 0 1 Seecomments Seecomments Maximum4devicessupported 1or2 formoredetails
device at2MSPSwith200-MHzCLK
+VBD AGND AGND +VBD
Multiple 1stDevice 1 0 0
devices orM1=1LVDS orM2=0LVDS(1) Maximum3devicessupported SeeFigures
1or2 3,4,14and6,15
icnascade 2ndTolast 1 0 1 +VBD AGND AGND +VBD at2MSPS formoredetails
device orM1=0LVDS orM2=0LVDS(1)
(1) Specifiedpolarityissuitablefora100-ΩdifferentialloadacrosstheLVDSoutputs.However,polaritycanbereversedtodoublethe
outputcurrentinordertosupporttwo100-Ωloadsonbothendsofthetransmissionlines,resultingin50-Ωnetload.
DETAILED DESCRIPTION
SAMPLE AND CONVERT
The sampling and conversion process is controlled by the CSTART (LVDS) or CONVST (CMOS) signal. Both
signals are functionally identical. The following diagrams show control with CONVST. The rising edge of
CONVST (or CSTART) starts the sample phase, if the conversion has completed and the device is in the wait
state. Figure 2 shows the case when the device is in the conversion phase at the rising edge of CONVST. In this
case,thesamplephasestartsimmediatelyattheendoftheconversionphaseandthereisnowaitstate.
CONVST
tw1 tw2
td1 td2 td4
BUSY
td3
Wait Sample Phase Conversion Phase Wait
tacq tcnv
Figure1. Sampleand ConvertWithWait (LessThan2MSPSThroughput)
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tw2
CONVST Not less than td1 to
avoid device entering
wait state
td2 td4
BUSY
td3
Sample Phase Conversion Phase Sample Phase
tacq tcnv
Figure2. Sampleand ConvertWithNoWaitorBacktoBack(2MSPSThroughput)
The device ends the sample phase and enters the conversion phase on the falling edge of CONVST (CSTART).
A high level on the BUSY output indicates an ongoing conversion. The device conversion time is fixed. The
falling edge of CONVST (CSTART) during the conversion phase aborts the ongoing conversion. A data read
after a conversion abort fetches invalid data. Valid data is only available after a sample phase and a conversion
phase has completed. The timing diagram for control with CSTART is similar to Figure 1 and Figure 2. Table 3
showstheequivalenttimingforcontrolwithCONVSTandCSTART.
Table3. CONVSTandCSTARTTimingControl
TIMINGCONTROLWITHCONVST TIMINGCONTROLWITHCSTART
t t
w1 w3
t t
w2 w4
t t
d1 d5
t t
d2 d6
t t
d3 d7
DATA READ OPERATION
The ADS8410 supports a 200-MHz serial LVDS interface for data read operation. The three signal LVDS
interface (SDO, CLK_O, and SYNC_O) is well suited for high-speed data transfers. An application with a single
device or multiple devices can be implemented with a daisy chain or cascade configuration. The following
sectionsdiscussdatareadtimingwhenasingledeviceisused.
DATAREADFORASINGLEDEVICE(SeeTable1forDeviceConfiguration)
For a single device, there are two possible read cycle starts: a data read cycle start during a wait or sample
phase or a data read cycle start at the end of a conversion phase. Read cycle end conditions can change
depending on MODE C/D selection. Figure 3 explains the data read cycle. The details of a read frame start with
the two previous listed conditions and a read cycle end with MODE C/D selection are explained in Figure 5 and
Figure6andFigure7andFigure8,respectively.
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