16-Bit, 1.25 MSPS, Pseudo-Bipolar Fully Differential Input Micro Power ADC PDF
Preview 16-Bit, 1.25 MSPS, Pseudo-Bipolar Fully Differential Input Micro Power ADC
(cid:2)(cid:17)(cid:14)(cid:14)(cid:20)(cid:2)(cid:14)(cid:13)(cid:18)(cid:12)(cid:0)(cid:4)(cid:14)(cid:13)(cid:8)(cid:17)(cid:7)(cid:16)(cid:15) (cid:10)(cid:14)(cid:13)(cid:11)(cid:0)(cid:5)(cid:9)(cid:19)(cid:6)(cid:15)(cid:0) (cid:3)(cid:12)(cid:15)(cid:16)(cid:14)(cid:17)(cid:11)(cid:9)(cid:12)(cid:16)(cid:15) ADS8406 SLAS426A–AUGUST2004–REVISEDDECEMBER2004 16-BIT, 1.25 MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICRO POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE FEATURES APPLICATIONS • Pseudo-Bipolar, FullyDifferentialInput, -V • DWDM REF toV • Instrumentation REF • 16-BitNMCat1.25MSPS • High-Speed,High-Resolution, ZeroLatency • – 2LSBINLMax, -1/+1.25LSBDNL DataAcquisitionSystems • 90dBSNR,-95dB THDat100kHzInput • TransducerInterface • Medical Instruments • ZeroLatency • Communications • Internal4.096V Reference • High-SpeedParallelInterface DESCRIPTION • Single5VAnalogSupply The ADS8406 is a 16-bit, 1.25 MHz A/D converter • WideI/OSupply:2.7Vto5.25V with an internal 4.096-V reference. The device in- • LowPower:155mWat1.25MHzTyp cludes a 16-bit capacitor-based SAR A/D converter • PinCompatibleWithADS8412/8402 with inherent sample and hold. The ADS8406 offers a full 16-bit interface and an 8-bit option where data is • 48-PinTQFPPackage readusingtwo8-bitreadcycles. The ADS8406 has a pseudo-bipolar, fully differential input. It is available in a 48-lead TQFP package and is characterized over the industrial -40(cid:176) C to 85(cid:176) C temperaturerange. HighSpeedSARConverterFamily Type/Speed 500kHz 580kHz 750MHZ 1.25MHz 2MHz 3MHz 4MHz 18BitPseudo-Diff ADS8383 ADS8381 ADS8371 ADS8401 ADS8411 16BitPseudo-Diff ADS8405 16BitPseudoBipolar, ADS8402 ADS8412 FullyDifferential ADS8406 14BitPseudo-Diff ADS7890(S) ADS7891 12BitPseudo-Diff ADS7881 SAR Output BYTE Latches 16-/8-Bit and Parallel DATA +IN + 3-State Output Bus _ CDAC Drivers −IN Comparator REFIN RESET Conversion CONVST 4.096-V and BUSY REFOUT Internal Clock Control Logic CS Reference RD Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2004,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters. ADS8406 www.ti.com SLAS426A–AUGUST2004–REVISEDDECEMBER2004 ORDERINGINFORMATION(1) MAXIMUM MAXIMUM NOMISSING PACKAGE TEMPERA- TRANSPORT INTEGRAL DIFFERENTIAL CODES PACKAGE ORDERING MODEL DESIG- TURE MEDIA LINEARITY LINEARITY RESOLUTION TYPE INFORMATION NATOR RANGE QUANTITY (LSB) (LSB) (BIT) Tapeandreel ADS8406IPFBT ADS8406I –4to+4 –2to+2 15 48Pin PFB –40(cid:176)Cto85(cid:176)C 250 TQFP Tapeandreel ADS8406IPFBR 1000 Tapeandreel ADS8406IBPFBT ADS8406IB –2to+2 –1to+1.25 16 48Pin PFB –40(cid:176)Cto85(cid:176)C 250 TQFP Tapeandreel ADS8406IBPFBR 1000 (1) Forthemostcurrentspecificationsandpackageinformation,refertoourwebsiteatwww.ti.com. ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerangeunlessotherwisenoted(1) UNIT +INtoAGND –0.4Vto+VA+0.1V Voltage –INtoAGND –0.4Vto+VA+0.1V +VAtoAGND –0.3Vto7V Voltagerange +VBDtoBDGND –0.3Vto7V +VAto+VBD –0.3Vto2.55V DigitalinputvoltagetoBDGND –0.3Vto+VBD+0.3V DigitaloutputvoltagetoBDGND –0.3Vto+VBD+0.3V T Operatingfree-airtemperaturerange –40(cid:176) Cto85(cid:176) C A T Storagetemperaturerange –65(cid:176) Cto150(cid:176) C stg Junctiontemperature(T max) 150(cid:176) C J Powerdissipation (TMax-T )/q J A JA TQFPpackage q thermalimpedance 86(cid:176) C/W JA Vaporphase(60sec) 215(cid:176) C Leadtemperature,soldering Infrared(15sec) 220(cid:176) C (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 2 ADS8406 www.ti.com SLAS426A–AUGUST2004–REVISEDDECEMBER2004 SPECIFICATIONS T =–40(cid:176) Cto85(cid:176) C,+VA=5V,+VBD=3Vor5V,V =4.096V,f =1.25MHz(unlessotherwisenoted) A ref SAMPLE PARAMETER TESTCONDITIONS MIN TYP MAX UNIT ANALOGINPUT Full-scaleinputvoltage (1) +IN– (–IN) –V V V ref ref +IN –0.2 V +0.2 ref Absoluteinputvoltage V –IN –0.2 V +0.2 ref Inputcapacitance 25 pF Inputleakagecurrent 0.5 nA SYSTEMPERFORMANCE Resolution 16 Bits ADS8406I 15 Nomissingcodes Bits ADS8406IB 16 ADS8406I –4 – 2 4 INL Integrallinearity (2)(3) LSB ADS8406IB –2 – 1 2 ADS8406I –2 – 1 2 DNL Differentiallinearity LSB ADS8406IB –1 – 0.5 1.25 ADS8406I –2.5 – 1 2.5 mV E Offseterror(4) O ADS8406IB –1.5 – 0.5 1.5 mV ADS8406I –0.12 0.12 E Gainerror(4)(5) %FS G ADS8406IB –0.098 0.098 Atdc(0.2VaroundV /2) 80 ref CMRR Commonmoderejectionratio dB +IN–(–IN)=1V at1MHz 80 pp At7FFFhoutputcode,+VA PSRR DCPowersupplyrejectionratio =4.75Vto5.25V,V = 2 LSB ref 4.096V (4) SAMPLINGDYNAMICS Conversiontime 500 650 ns Acquisitiontime 150 ns Throughputrate 1.25 MHz Aperturedelay 2 ns Aperturejitter 25 ps Stepresponse 100 ns Overvoltagerecovery 100 ns DYNAMICCHARACTERISTICS V =8V at100kHz –95 THD Totalharmonicdistortion (6) IN pp dB V =8V at500kHz –90 IN pp SNR Signal-to-noiseratio V =8V at100kHz 90 dB IN pp SINAD Signal-to-noise+distortion V =8V at100kHz 88 dB IN pp V =8V at100kHz 95 IN pp SFDR Spuriousfreedynamicrange dB V =8V at500kHz 93 IN pp -3dBSmallsignalbandwidth 5 MHz EXTERNALVOLTAGEREFERENCEINPUT ReferencevoltageatREFIN,V 2.5 4.096 4.2 V ref Referenceresistance (7) 500 kW (1) Idealinputspan,doesnotincludegainoroffseterror. (2) LSBmeansleastsignificantbit (3) ThisisendpointINL,notbestfit. (4) Measuredrelativetoanidealfull-scaleinput[+IN–(–IN)]of8.192V (5) Thisspecificationdoesnotincludetheinternalreferencevoltageerroranddrift. (6) Calculatedonthefirstnineharmonicsoftheinputfrequency (7) Canvary– 20% 3 ADS8406 www.ti.com SLAS426A–AUGUST2004–REVISEDDECEMBER2004 SPECIFICATIONS (continued) T =–40(cid:176) Cto85(cid:176) C,+VA=5V,+VBD=3Vor5V,V =4.096V,f =1.25MHz(unlessotherwisenoted) A ref SAMPLE PARAMETER TESTCONDITIONS MIN TYP MAX UNIT INTERNALREFERENCEOUTPUT From95%(+VA)with1-µF Internalreferencestart-uptime 120 ms storagecapacitor V Referencevoltage IOUT=0 4.065 4.096 4.13 V ref Sourcecurrent Staticload 10 µA Lineregulation +VA=4.75to5.25V 0.6 mV Drift IOUT=0 36 PPM/(cid:176) C DIGITALINPUT/OUTPUT Logicfamily—CMOS V Highlevelinputvoltage I =5µA +VBD–1 +VBD+0.3 IH IH V Lowlevelinputvoltage I =5µA –0.3 0.8 IL IL V V Highleveloutputvoltage I =2TTLloads +VBD–0.6 +VBD OH OH V Lowleveloutputvoltage I =2TTLloads 0 0.4 OL OL Dataformat—2'scomplement POWERSUPPLYREQUIREMENTS +VBD 2.7 3 5.25 V Powersupplyvoltage +VA 4.75 5 5.25 V Supplycurrent,+VA(8) f =1.25MHz 31 34 mA s P Powerdissipation(8) f =1.25MHz 155 170 mW D s TEMPERATURERANGE T Operatingfree-airtemperature –40 85 (cid:176) C A (8) Thisincludesonly+VAcurrent.+VBDcurrentistypically1mAwith5-pFloadcapacitanceonoutputpins. 4 ADS8406 www.ti.com SLAS426A–AUGUST2004–REVISEDDECEMBER2004 TIMING CHARACTERISTICS Allspecificationstypicalat–40(cid:176) Cto85(cid:176) C,+VA=+VBD=5V (1)(2)(3) PARAMETER MIN TYP MAX UNIT t Conversiontime 500 650 ns CONV t Acquisitiontime 150 ns ACQ t CONVSTlowtoBUSYhigh 40 ns pd1 t Propagationdelaytime,endofconversiontoBUSYlow 5 ns pd2 t Pulseduration,CONVSTlow 20 ns w1 t Setuptime,CSlowtoCONVSTlow 0 ns su1 t Pulseduration,CONVSThigh 20 ns w2 CONVSTfallingedgejitter 10 ps t Pulseduration,BUSYsignallow Min(t ) ns w3 ACQ t Pulseduration,BUSYsignalhigh 610 ns w4 Holdtime,Firstdatabusdatatransition(RDlow,orCSlowfor t 40 ns h1 readcycle,orBYTEinputchanges)afterCONVSTlow Delaytime,CSlowtoRDlow(orBUSYlowtoRDlowwhenCS= t 0 ns d1 0) t Setuptime,RDhightoCShigh 0 ns su2 t Pulseduration,RDlowtime 50 ns w5 t Enabletime,RDlow(orCSlowforreadcycle)todatavalid 20 ns en t Delaytime,dataholdfromRDhigh 0 ns d2 t Delaytime,BYTErisingedgeorfallingedgetodatavalid 2 20 ns d3 t Pulseduration,RDhigh 20 ns w6 t Pulseduration,CShightime 20 ns w7 Holdtime,lastRD(orCSforreadcycle)risingedgetoCONVST t 50 ns h2 fallingedge t Setuptime,BYTEtransitiontoRDfallingedge 0 ns su3 t Holdtime,BYTEtransitiontoRDfallingedge 0 ns h3 Disabletime,RDhigh(CShighforreadcycle)to3-stateddata t 20 ns dis bus t Delaytime,endofconversiontoMSBdatavalid 10 ns d5 Bytetransitionsetuptime,fromBYTEtransitiontonextBYTE t 50 ns su4 transition t Delaytime,CSrisingedgetoBUSYfallingedge 50 ns d6 t Delaytime,BUSYfallingedgetoCSrisingedge 50 ns d7 Setuptime,fromthefallingedgeofCONVST(usedtostartthe validconversion)tothenextfallingedgeofCONVST(whenCS= t 60 500 ns su(AB) 0andCONVSTusedtoabort)ortothenextfallingedgeofCS (whenCSisusedtoabort) Setuptime,fallingedgeofCONVSTtoreadvaliddata(MSB)from t MAX(t )+MAX(t ) ns su5 currentconversion CONV d5 Holdtime,data(MSB)frompreviousconversionholdvalidfrom t MIN(t ) ns h4 fallingedgeofCONVST CONV (1) Allinputsignalsarespecifiedwitht =t =5ns(10%to90%of+VBD)andtimedfromavoltagelevelof(V +V )/2. r f IL IH (2) Seetimingdiagrams. (3) Alltimingsaremeasuredwith20-pFequivalentloadsonalldatabitsandBUSYpins. 5 ADS8406 www.ti.com SLAS426A–AUGUST2004–REVISEDDECEMBER2004 TIMING CHARACTERISTICS Allspecificationstypicalat–40(cid:176) Cto85(cid:176) C,+VA=5V,+VBD=3V(1)(2)(3) PARAMETER MIN TYP MAX UNIT t Conversiontime 500 650 ns CONV t Acquisitiontime 150 ns ACQ t CONVSTlowtoBUSYhigh 50 ns pd1 t Propagationdelaytime,endofconversiontoBUSYlow 10 ns pd2 t Pulseduration,CONVSTlow 20 ns w1 t Setuptime,CSlowtoCONVSTlow 0 ns su1 t Pulseduration,CONVSThigh 20 ns w2 CONVSTfallingedgejitter 10 ps t Pulseduration,BUSYsignallow Min(t ) ns w3 ACQ t Pulseduration,BUSYsignalhigh 610 ns w4 Holdtime,firstdatabustransition(RDlow,orCSlowforread t 40 ns h1 cycle,orBYTEorBUS16/16inputchanges)afterCONVSTlow Delaytime,CSlowtoRDlow(orBUSYlowtoRDlowwhenCS= t 0 ns d1 0) t Setuptime,RDhightoCShigh 0 ns su2 t Pulseduration,RDlow 50 ns w5 t Enabletime,RDlow(orCSlowforreadcycle)todatavalid 30 ns en t Delaytime,dataholdfromRDhigh 0 ns d2 t Delaytime,BYTErisingedgeorfallingedgetodatavalid 2 30 ns d3 t Pulseduration,RDhightime 20 ns w6 t Pulseduration,CShightime 20 ns w7 Holdtime,lastRD(orCSforreadcycle)risingedgetoCONVST t 50 ns h2 fallingedge t Setuptime,BYTEtransitiontoRDfallingedge 0 ns su3 t Holdtime,BYTEtransitiontoRDfallingedge 0 ns h3 t Disabletime,RDhigh(CShighforreadcycle)to3-stateddatabus 30 ns dis t Delaytime,endofconversiontoMSBdatavalid 20 ns d5 Bytetransitionsetuptime,fromBYTEtransitiontonextBYTE t 50 ns su4 transition t Delaytime,CSrisingedgetoBUSYfallingedge 50 ns d6 t Delaytime,BUSYfallingedgetoCSrisingedge 50 ns d7 Setuptime,fromthefallingedgeofCONVST(usedtostartthe validconversion)tothenextfallingedgeofCONVST(whenCS=0 t 70 500 ns su(AB) andCONVSTusedtoabort)ortothenextfallingedgeofCS (whenCSisusedtoabort) Setuptime,fallingedgeofCONVSTtoreadvaliddata(MSB)from t MAX(t )+MAX(t ) ns su5 currentconversion CONV d5 Holdtime,data(MSB)frompreviousconversionholdvalidfrom t MIN(t ) ns h4 fallingedgeofCONVST CONV (1) Allinputsignalsarespecifiedwitht =t =5ns(10%to90%of+VBD)andtimedfromavoltagelevelof(V +V )/2. r f IL IH (2) Seetimingdiagrams. (3) Alltimingsaremeasuredwith20-pFequivalentloadsonalldatabitsandBUSYpins. 6 ADS8406 www.ti.com SLAS426A–AUGUST2004–REVISEDDECEMBER2004 PIN ASSIGNMENTS PFB PACKAGE (TOP VIEW) D D YN D N SG B 0 1 2 34 5 6 7 G UD V B B B BB B B B D BB + D D D DD D D D B 36 3534 3332 3130 2928 27 26 25 +VBD 37 24 +VBD RESET 38 23 DB8 BYTE 39 22 DB9 CONVST 40 21 DB10 RD 41 20 DB11 CS 42 19 DB12 +VA 43 18 DB13 AGND 44 17 DB14 AGND 45 16 DB15 +VA 46 15 AGND REFM 47 14 AGND REFM 48 13 +VA 1 2 3 4 5 6 7 8 9 10 1112 NT C A D N ND A A D D EFIOU N +V GN +I -IGN +V +V GN GN RF A A A A E R NC - No connection 7 ADS8406 www.ti.com SLAS426A–AUGUST2004–REVISEDDECEMBER2004 TerminalFunctions NAME NO. I/O DESCRIPTION AGND 5,8,11,12,14, – Analogground 15,44,45 BDGND 25,35 – Digitalgroundforbusinterfacedigitalsupply BUSY 36 O Statusoutput.Highwhenaconversionisinprogress. BYTE 39 I Byteselectinput.Usedfor8-bitbusreading.0:Nofoldback1:LowbyteD[7:0]ofthe16most significantbitsisfoldedbacktohighbyteofthe16mostsignificantpinsDB[15:8]. CONVST 40 I Convertstart.Thefallingedgeofthisinputendstheacquisitionperiodandstartsthehold period. CS 42 I Chipselect.Thefallingedgeofthisinputstartstheacquisitionperiod. 8-BitBus 16-BitBus DataBus BYTE=0 BYTE=1 BYTE=0 DB15 16 O D15(MSB) D7 D15(MSB) DB14 17 O D14 D6 D14 DB13 18 O D13 D5 D13 DB12 19 O D12 D4 D12 DB11 20 O D11 D3 D11 DB10 21 O D10 D2 D10 DB9 22 O D9 D1 D9 DB8 23 O D8 D0(LSB) D8 DB7 26 O D7 Allones D7 DB6 27 O D6 Allones D6 DB5 28 O D5 Allones D5 DB4 29 O D4 Allones D4 DB3 30 O D3 Allones D3 DB2 31 O D2 Allones D2 DB1 32 O D1 Allones D1 DB0 33 O D0(LSB) Allones D0(LSB) –IN 7 I Invertinginputchannel +IN 6 I Noninvertinginputchannel NC 3 – Noconnection REFIN 1 I Referenceinput REFM 47,48 I Referenceground REFOUT 2 O Referenceoutput.Add1-µFcapacitorbetweentheREFOUTpinandREFMpinwheninternal referenceisused. RESET 38 I Currentconversionisabortedandoutputlatchesarecleared(settozeros)whenthispinis assertedlow.RESETworksindependantlyofCS. RD 41 I Synchronizationpulsefortheparalleloutput.WhenCSislow,thisservesastheoutputenable andputsthepreviousconversionresultonthebus. +VA 4,9,10,13,43, – Analogpowersupplies,5-Vdc 46 +VBD 24,34,37 – Digitalpowersupplyforbus 8 ADS8406 www.ti.com SLAS426A–AUGUST2004–REVISEDDECEMBER2004 TIMING DIAGRAMS tw1 tw2 CONVST (used in normal conversion) tcycle CONVST (used in ABORT) tsu(AB) tsu(AB) tpd1 tw4 tpd2 tpd1 tw3 BUSY tsu1 tw7 td7 CS td6 CONVERT† tCONV tCONV SAMPLING† (When CS Toggle) tACQ BYTE tsu4 th1 td1 tsu2 th2 RD Invalid Invalid Data to Previous Conversion Current Conversion be read† th4 tsu5 ten tdis Hi−Z Hi−Z DB[15:8] D [15:8] D [7:0] Hi−Z Hi−Z DB[7:0] D [7:0] †Signal internal to device Figure1.Timingfor ConversionandAcquisitionCyclesWithCSandRDToggling 9 ADS8406 www.ti.com SLAS426A–AUGUST2004–REVISEDDECEMBER2004 TIMING DIAGRAMS (continued) tw1 tw2 CONVST (used in normal conversion) tcycle CONVST (used in ABORT) tsu(AB) tsu(AB) tpd1 tpd2 tw4 tw3 BUSY tsu1 tw7 td7 CS td6 CONVERT† tCONV tCONV SAMPLING† (When CS Toggle) tACQ BYTE th1 ten tsu4th2 RD = 0 ten tdis Invalid tdis Invalid Data to be read† Previous Conversion Current Conversion th4 tsu5 Previous Repeated Hi−Z Hi−Z Hi−Z DB[15:8] D [15:8] D [15:8] D [7:0] D [15:8] Previous Repeated Hi−Z Hi−Z Hi−Z DB[7:0] D [7:0] D [7:0] D [7:0] †Signal internal to device ten Figure2.Timing forConversionandAcquisitionCyclesWithCSToggling, RDTiedtoBDGND 10
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