14/12 Bit, 250/210 MSPS ADC with DDR LVDS and Parallel CMOS Outputs PDF
Preview 14/12 Bit, 250/210 MSPS ADC with DDR LVDS and Parallel CMOS Outputs
ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com..................................................................................................................................................... SLWS211B–JULY2008–REVISEDOCTOBER2008 14/12-Bit, 250/210 MSPS ADCs With DDR LVDS and Parallel CMOS Outputs FEATURES 1 • MaximumSampleRate:250MSPS DESCRIPTION • 14-BitResolution–ADS614X ADS614X (ADS612X) is a family of 14-bit (12-bit) A/D • 12-BitResolution–ADS612X converters with sampling rates up to 250 MSPS. It combines high dynamic performance and low power • 687mWTotalPowerDissipationat250MSPS consumption in a compact 48 QFN package. This • DoubleDataRate(DDR)LVDSandParallel makes it well-suited for multicarrier, wide band-width CMOSOutputOptions communicationsapplications. • ProgrammableFineGainupto6dB for ADS614X/2X has fine gain options that can be used SNR/SFDRTrade-Off to improve SFDR performance at lower full-scale • DCOffsetCorrection input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR • SupportsInputClockAmplitudeDownto400 LVDS (Double Data Rate) and parallel CMOS digital mV Differential PP output interfaces are available. At lower sampling • InternalandExternalReferenceSupport rates,the ADC automatically operates at scaled down • 48-QFNPackage(7mm×7mm) power withnoloss inperformance. • PinCompatiblewithADS5547Family It includes internal references while the traditional reference pins and associated decoupling capacitors APPLICATIONS have been eliminated. Nevertheless, the device can • Multicarrier,WideBand-Width also be driven with an external reference. The device is specified over the industrial temperature range Communications (–40°Cto85°C). • WirelessMulti-carrierCommunications Infrastructure 250MSPS 210MSPS • SoftwareDefinedRadio ADS614X ADS6149 ADS6148 • PowerAmplifierLinearization 14-BitFamily • 802.16d/e ADS612X ADS6129 ADS6128 12-BitFamily • TestandMeasurementInstrumentation • HighDefinition Video • MedicalImaging • RadarSystems 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2008,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters. ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B–JULY2008–REVISEDOCTOBER2008..................................................................................................................................................... www.ti.com Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. ADS614X BLOCK DIAGRAM D D D D D N D N V G V G R R A A D D DDR LVDS Interface CLKP CLKOUTP CLOCKGEN CLKM CLKOUTM D0_D1_P D0_D1_M D2_D3_P D2_D3_M D4_D5_P D4_D5_M INP Sample DDR D6_D7_P and 14-BitADC Serializer Hold D6_D7_M INM D8_D9_P D8_D9_M D10_D11_P D10_D11_M Control VCM Reference Interface D12_D13_P D12_D13_M OVR_SDOUT ADS6149/48 T K N A S E E L E T F D S C S A D O RE S SD M B0095-06 2 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):ADS6149/ADS6129ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com..................................................................................................................................................... SLWS211B–JULY2008–REVISEDOCTOBER2008 ADS612X BLOCK DIAGRAM D D D D D N D N V G V G R R A A D D DDR LVDS Interface CLKP CLKOUTP CLOCKGEN CLKM CLKOUTM D0_D1_P D0_D1_M D2_D3_P D2_D3_M D4_D5_P D4_D5_M INP Sample DDR D6_D7_P and 12-BitADC Serializer Hold D6_D7_M INM D8_D9_P D8_D9_M D10_D11_P D10_D11_M Control VCM Reference Interface OVR_SDOUT ADS6129/28 T K N A S E E L E T F D S C S A D O RE S SD M B0095-07 Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):ADS6149/ADS6129ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B–JULY2008–REVISEDOCTOBER2008..................................................................................................................................................... www.ti.com PACKAGE/ORDERINGINFORMATION(1)(2) SPECIFIED PACKAGE LEAD/BALL PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE-LEAD TEMPERATURE DESIGNATOR FINISH MARKING NUMBER MEDIA,QUANTITY RANGE ADS614x ADS6149IRGZR ADS6149 AZ6149 ADS6149IRGZT QFN-48 RGZ –40°Cto85°C CuNiPdAu Tapeandreel ADS6148IRGZR ADS6148 AZ6148 ADS6148IRGZT ADS612x ADS6129IRGZR ADS6129 AZ6129 ADS6129IRGZT QFN-48 RGZ –40°Cto85°C CuNiPdAu Tapeandreel ADS6128IRGZR ADS6128 AZ6128 ADS6128IRGZT (1) Forthermalpadsizeonthepackage,seethemechanicaldrawingsattheendofthisdatasheet.q =25.41°C/W(0LFMairflow), JA q =16.5°C/Wwhenusedwith2oz.coppertraceandpadsoldereddirectlytoaJEDECstandardfourlayer3inx3in(7.62cmx7.62 JC cm)PCB. (2) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. ABSOLUTE MAXIMUM RATINGS(1) VALUE UNIT Supplyvoltagerange,AVDD –0.3Vto3.9 V Supplyvoltagerange,DRVDD –0.3Vto2.2 V VoltagebetweenAGNDandDRGND –0.3to0.3 V VoltagebetweenAVDDtoDRVDD(whenAVDDleadsDRVDD) 0to3.3 V V VoltagebetweenDRVDDtoAVDD(whenDRVDDleadsAVDD) –1.5to1.8 V I Voltageappliedtoexternalpin,VCM(inexternalreferencemode) –0.3to2.0 V Voltageappliedtoanaloginputpins-INP,INM –0.3Vtominimum V (3.6,AVDD+0.3V) Voltageappliedtoinputpins-CLKP,CLKM(2),RESET,SCLK,SDATA,SEN,DFSand –0.3VtoAVDD+0.3V V MODE T Operatingfree-airtemperaturerange –40to85 °C A T Operatingjunctiontemperaturerange 125 °C J T Storagetemperaturerange –65to150 °C stg (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolutemaximumratedconditionsforextendedperiodsmayaffectdevicereliability. (2) WhenAVDDisturnedoff,itisrecommendedtoswitchofftheinputclock(orensurethevoltageonCLKP,CLKMis<|0.3V|.This preventstheESDprotectiondiodesattheclockinputpinsfromturningon. 4 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):ADS6149/ADS6129ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com..................................................................................................................................................... SLWS211B–JULY2008–REVISEDOCTOBER2008 RECOMMENDED OPERATING CONDITIONS overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN TYP MAX UNIT SUPPLIES AVDD Analogsupplyvoltage 3 3.3 3.6 V DRVDD Digitalsupplyvoltage 1.7 1.8 1.9 V ANALOGINPUTS Differentialinputvoltagerange 2 V pp Inputcommon-modevoltage 1.5±0.1 V VoltageappliedonCMinexternalreferencemode 1.5±0.05 V Maximumanaloginputfrequencywith2V inputamplitude(1) 500 MHz PP Maximumanaloginputfrequencywith1V inputamplitude(1) 800 MHz PP CLOCKINPUT ADS6149/ADS6129 1 250 Inputclocksamplerate MSPS ADS6148/ADS6128 1 210 Sinewave,ac-coupled 0.3 1.5 InputClockamplitudedifferential LVPECL,ac-coupled 1.6 Vpp (VCLKP–VCLKM) LVDS,ac-coupled 0.7 LVCMOS,single-ended,ac-coupled 3.3 V Inputclockdutycycle 40% 50% 60% DIGITALOUTPUTS C MaximumexternalloadcapacitancefromeachoutputpintoDRGND 5 pF L R DifferentialloadresistancebetweentheLVDSoutputpairs(LVDSmode) 100 Ω L T Operatingfree-airtemperature –40 85 °C A (1) SeetheTheoryofOperationintheapplicationsection. Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):ADS6149/ADS6129ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B–JULY2008–REVISEDOCTOBER2008..................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS – ADS614X and ADS612X Typicalvaluesareat25°C,AVDD=3.3V,DRVDD=1.8V,50%clockdutycycle,–1dBFSdifferentialanaloginput,internal referencemodeunlessotherwisenoted. MinandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=3.3V,DRVDD=1.8V MIN MAX ADS6149/ADS6129 ADS6148/ADS6128 PARAMETER 250MSPS 210MSPS UNIT MIN TYP MAX MIN TYP MAX ANALOGINPUT Differentialinputvoltagerange 2 2 V PP Differentialinputresistance(atdc),SeeFigure97 >1 >1 MΩ Differentialinputcapacitance,SeeFigure98 3.5 3.5 pF AnalogInputBandwidth 700 700 MHz AnalogInputcommonmodecurrent(perinputpin) 2 2 m A/MSPS VCMCommonmodeoutputvoltage 1.5 1.5 V VCMoutputcurrentcapability ±4 ±4 mA DCACCURACY Offseterror –15 ±2 15 –15 ±2 15 mV Temperaturecoefficientofoffseterror 0.005 0.005 mV/°C Variationofoffseterrorwithsupply 0.3 0.3 mV/V E Gainerrorduetointernalreferenceinaccuracyalone –1.25 ±0.2 1.25 –1.25 ±0.2 1.25 %FS GREF E Gainerrorofchannelalone 0.2 0.2 %FS GCHAN TemperaturecoefficientofE .001 .001 Δ%/°C GCHAN POWERSUPPLY I Analogsupplycurrent 170 155 mA AVDD Outputbuffersupplycurrent,LVDSinterfacewith100Ωexternal 70 65 mA termination I DRVDD Outputbuffersupplycurrent,CMOSinterfaceFin=3MHz(1), 56 48 mA 10-pFexternalloadcapacitance Analogpower 561 630 510 570 mW DigitalpowerLVDSinterface 126 160 118 153 mW DigitalpowerCMOSinterface,Fin=3MHz(2),10-pFexternal 101 87 mW loadcapacitance Globalpowerdown 20 50 20 50 mW Standby 120 120 mW (1) InCMOSmode,theDRVDDcurrentscaleswiththesamplingfrequency,theloadcapacitanceonoutputpins,inputfrequencyandthe supplyvoltage(seeFigure91andCMOSinterfacepowerdissipationinapplicationsection). (2) ThemaximumDRVDDcurrentwithCMOSinterfacedependsontheactualloadcapacitanceonthedigitaloutputlines.Notethatthe maximumrecommendedloadcapacitanceoneachdigitaloutputlineis10pF. 6 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):ADS6149/ADS6129ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com..................................................................................................................................................... SLWS211B–JULY2008–REVISEDOCTOBER2008 ELECTRICAL CHARACTERISTICS – ADS6149 and ADS6148 Typicalvaluesareat25°C,AVDD=3.3V,DRVDD=1.8V,50%clockdutycycle,–1dBFSdifferentialanaloginput,internal referencemodeunlessotherwisenoted. MinandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=3.3V,DRVDD=1.8V MIN MAX ADS6149 ADS6148 PARAMETER 250MSPS 210MSPS UNIT MIN TYP MAX MIN TYP MAX Fin=20MHz 73.4 73.4 Fin=80MHz 72.7 72.7 SNR Fin=100MHz 72.3 72.3 dBFS Signaltonoiseratio,LVDS Fin=170MHz 69 71.3 69.7 71.2 Fin=300MHz 69 69 Fin=20MHz 73.2 73.3 Fin=80MHz 72.4 72.4 SINAD Fin=100MHz 71.9 71.8 dBFS Signaltonoiseanddistortionratio,LVDS Fin=170MHz 68 70.6 68.7 70.9 Fin=300MHz 68 68.2 ENOB Fin=170MHz 11 11.4 11.1 11.5 LSB Effectivenumberofbits DNL –0.95 ±0.4 2 –0.95 ±0.4 2 LSB Differentialnon-linearity INL –5 ±2 5 –5 ±2 5 LSB Integratednon-linearity ELECTRICAL CHARACTERISTICS – ADS6129 and ADS6128 Typicalvaluesareat25°C,AVDD=3.3V,DRVDD=1.8V,50%clockdutycycle,–1dBFSdifferentialanaloginput,internal referencemodeunlessotherwisenoted. MinandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=3.3V,DRVDD=1.8V MIN MAX ADS6129 ADS6128 PARAMETER 250MSPS 210MSPS UNIT MIN TYP MAX MIN TYP MAX Fin=20MHz 70.7 70.9 Fin=80MHz 70.5 70.5 SNR, Fin=100MHz 70.1 70.1 dBFS Signaltonoiseratio,LVDS Fin=170MHz 67.5 69.5 67.7 69.5 Fin=300MHz 67.8 67.9 Fin=20MHz 70.6 70.8 Fin=80MHz 70.4 70.4 SINAD Fin=100MHz 69.8 69.8 dBFS Signaltonoiseanddistortionratio,LVDS Fin=170MHz 66.5 69.2 66.7 69.3 Fin=300MHz 67.2 67.3 ENOB, Fin=170MHz 10.8 11.2 10.8 11.2 LSB Effectivenumberofbits DNL –0.5 ±0.2 1 –0.5 ±0.2 1.0 LSB Differentialnon-linearity INL –2.5 ±1 2.5 –2.5 ±1 2.5 LSB Integratednon-linearity Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):ADS6149/ADS6129ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B–JULY2008–REVISEDOCTOBER2008..................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS – ADS614x and ADS612x Typicalvaluesareat25°C,AVDD=3.3V,DRVDD=1.8V,50%clockdutycycle,–1dBFSdifferentialanaloginput,internal referencemodeunlessotherwisenoted. MinandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=3.3V,DRVDD=1.8V MIN MAX ADS6149/ADS6129 ADS6148/ADS6128 PARAMETER 250MSPS 210MSPS UNIT MIN TYP MAX MIN TYP MAX Fin=20MHz 92 92 Fin=80MHz 86 82 SFDR Fin=100MHz 85 81 dBc SpuriousFreeDynamicRange Fin=170MHz 74 82 74 83 Fin=300MHz 76 76 Fin=10MHz 89 88.5 Fin=20MHz 83 80 THD Fin=80MHz 82 79 dBc TotalHarmonicDistortion Fin=170MHz 71 79 71 80 Fin=300MHz 73 73 Fin=20MHz 94 94 Fin=80MHz 90 88 HD2, Fin=100MHz 88 88 dBc SecondHarmonicDistortion Fin=170MHz 74 84 74 84 Fin=300MHz 76 76 Fin=20MHz 93 92 Fin=80MHz 86 82 HD3 Fin=100MHz 85 81 dBc ThirdHarmonicDistortion Fin=170MHz 74 82 74 83 Fin=300MHz 76 76 Fin=20MHz 96 96 Fin=80MHz 94 94 WorstSpur Fin=100MHz 94 94 dBc Otherthansecond,thirdharmonics Fin=170MHz 92 92 Fin=300MHz 90 90 F1=46MHz,F2=50MHz, 94 95 IMD Eachtoneat–7dBFS dBFS 2-Toneinter-modulationdistortion F1=185MHz,F2=190MHz, 90 90 Eachtoneat–7dBFS Recoverytowithin1%(offinalvalue)for clock Inputoverloadrecovery 1 1 6-dBoverloadwithsinewaveinput cycles PSRR For100mV signalonAVDDsupply 25 25 dB ACpowersupplyrejectionratio PP 8 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):ADS6149/ADS6129ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com..................................................................................................................................................... SLWS211B–JULY2008–REVISEDOCTOBER2008 DIGITAL CHARACTERISTICS – ADS614x and ADS612x TheDCspecificationsrefertotheconditionwherethedigitaloutputsarenotswitching,butarepermanentlyatavalidlogic level0or1.AVDD=3.3V,DRVDD=1.8V ADS6149/ADS6148/ PARAMETER TESTCONDITIONS ADS6129/ADS6128 UNIT MIN TYP MAX DIGITALINPUTS–RESET,SCLK,SDATA,SEN(1) High-levelinputvoltage Alldigitalinputssupport1.8Vand3.3VCMOSlogic 1.3 V Low-levelinputvoltage levels 0.4 V SDATA,SCLK(2) VHIGH=3.3V 16 High-levelinputcurrent m A SEN(3) VHIGH=3.3V 10 SDATA,SCLK VLOW=0V 0 Low-levelinputcurrent m A SEN VLOW=0V –20 Inputcapacitance 4 pF DIGITALOUTPUTS–CMOSINTERFACE(PinsD0toD13andOVR_SDOUT) High-leveloutputvoltage DRVDD V Low-leveloutputvoltage 0 V Outputcapacitance(internaltodevice) 2 pF DIGITALOUTPUTS–LVDSINTERFACE(PinsD0_D1_P/MtoD12_D13_P/M)(4) V ,High-leveloutputvoltage(5) 275 350 425 mV ODH V ,Low-leveloutputvoltage(5) –425 –350 –275 mV ODL V ,Outputcommon-modevoltage 1 1.2 1.3 V OCM Capacitanceinsidethedevice,fromeitheroutputto Outputcapacitance 2 pF ground (1) SCLK,SDATA,SENfunctionasdigitalinputpinsinserialconfigurationmode. (2) SDATA,SCLKhaveinternal200kΩpull-downresistor (3) SENhasinternal100kΩpull-upresistortoAVDD.Sincethepull-upisweak,SENcanalsobedrivenby1.8Vor3.3VCMOSbuffers. (4) OVR_SDOUThasCMOSoutputlogiclevels,determinedbyDRVDDvoltage. (5) Withexternal100Ωtermination DDn_nD_Dn+n1+_1P_P Logic 0 Logic 1 (1) (1) V =–350 mV V = 350 mV ODL ODH Dn_Dn+1_M Dn_Dn+1_M VOOCVCMM GGNNDD T0399-01 Figure1.LVDSVoltageLevels Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):ADS6149/ADS6129ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B–JULY2008–REVISEDOCTOBER2008..................................................................................................................................................... www.ti.com TIMING REQUIREMENTS – LVDS AND CMOS MODES(1) Typicalvaluesareat25°C,AVDD=3.3V,DRVDD=1.8V,samplingfrequency=250MSPS,sinewaveinputclock, C =5pF(2),R =100Ω(3),LOWSPEEDmodedisabled,unlessotherwisenoted. LOAD LOAD MinandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=3.3V,DRVDD=1.7Vto MIN MAX 1.9V. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Thedelayintimebetweentherisingedgeoftheinputsamplingclockand ta Aperturedelay theactualtimeatwhichthesamplingoccurs 0.7 1.2 1.7 ns tj Aperturejitter 170 fsrms TimetovaliddataaftercomingoutofSTANDBYmode 0.3 1 m s TimetovaliddataaftercomingoutofPDNGLOBALmode 25 100 Wake-uptime clock Timetovaliddataafterstoppingandrestartingtheinputclock 10 cycles ADCLatency(4) Default,afterreset 18 clock cycles DDRLVDSMODE(5) tsu Datasetuptime Datavalid(6)tozero-crossingofCLKOUTP 0.8 1.2 ns th Dataholdtime Zero-crossingofCLKOUTtodatabecominginvalid(6) 0.25 0.6 ns tPDI Clockpropagationdelay Inputclockrisingedgecross-overtooutputclockrisingedgecross-over 0.2×ts+tdelay ns 100MSPS≤Samplingfrequency≤250MSPS tdelay 5.0 6.2 7.5 ns Dutycycleofdifferentialclock,(CLKOUTP–CLKOUTM) LVDSbitclockdutycycle 52% 100MSPS≤Samplingfrequency≤250MSPS Risetimemeasuredfrom–100mVto100mV tRISE, Datarisetime, Falltimemeasuredfrom100mVto–100mV 0.08 0.14 0.2 ns tFALL Datafalltime 1MSPS≤Samplingfrequency≤250MSPS Risetimemeasuredfrom–100mVto100mV tCLKRISE, Outputclockrisetime, Falltimemeasuredfrom100mVto–100mV 0.08 0.14 0.2 ns tCLKFALL Outputclockfalltime 1MSPS≤Samplingfrequency≤250MSPS tOE Outputenable(OE)todatadelay TimetovaliddataafterOEbecomesactive 40 ns PARALLELCMOSMODE(7) tSTART Inputclocktodatadelay Inputclockrisingedgecross-overtostartofdatavalid(8) 3.2 ns tDV Datavalidtime Timeintervalofvaliddata(8) 0.7 1.5 ns tPDI Clockpropagationdelay Inputclockrisingedgecross-overtooutputclockrisingedgecross-over 0.78×ts+tdelay 100MSPS≤Samplingfrequency≤150MSPS tdelay 5 6.5 8 ns Dutycycleofdifferentialclock,(CLKOUT) Outputclockdutycycle 50% 100MSPS≤Samplingfrequency≤150MSPS tRISE, Datarisetime, Risetimemeasuredfrom20%to80%ofDRVDD, tFALL Datafalltime Falltimemeasuredfrom80%to20%ofDRVDD, 0.7 1.2 2 ns 1MSPS≤Samplingfrequency≤250MSPS Risetimemeasuredfrom20%to80%ofDRVDD, tCLKRISE, Outputclockrisetime, Falltimemeasuredfrom80%to20%ofDRVDD, 0.5 1 1.5 ns tCLKFALL Outputclockfalltime 1MSPS≤Samplingfrequency≤150MSPS tOE Outputenable(OE)todatadelay TimetovaliddataafterOEbecomesactive 20 ns (1) Timingparametersarespecifiedbydesignandcharacterizationandnottestedinproduction. (2) C istheeffectiveexternalsingle-endedloadcapacitancebetweeneachoutputpinandground LOAD (3) R isthedifferentialloadresistancebetweentheLVDSoutputpair. LOAD (4) Athigherfrequencies,t isgreaterthanoneclockperiodandoveralllatency=ADClatency+1. PDI (5) Measurementsaredonewithatransmissionlineof100Ωcharacteristicimpedancebetweenthedeviceandtheload.Setupandhold timespecificationstakeintoaccounttheeffectofjitterontheoutputdataandclock. (6) DatavalidreferstoLOGICHIGHof+100mVandLOGICLOWof–100mV. (7) ForFs>150MSPS,itisrecommendedtouseexternalclockfordatacaptureandNOTthedeviceoutputclocksignal(CLKOUT). (8) DatavalidreferstoLOGICHIGHof1.26VandLOGICLOWof0.54V. 10 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):ADS6149/ADS6129ADS6148/ADS6128
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