14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS datasheet

67 Pages·2017·2.26 MB·English

ADS6145, ADS6144
ADS6143, ADS6142
www.ti.com
SLWS198B–JULY2007–REVISEDMARCH2008
14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
FEATURES • RadarSystems
1
• MaximumSampleRate:125MSPS
DESCRIPTION
• 14-BitResolutionwithNo MissingCodes
• 3.5dBCoarseGainandupto6dB ADS6145/ADS6144/ADS6143/ADS6142 (ADS614X)
are a family of 14-bit A/D converters with sampling
ProgrammableFineGainforSNR/SFDR
frequencies up to 125 MSPS. The high performance
Trade-Off
and low power consumption of the ADS614X are
• ParallelCMOS andDoubleDataRate (DDR) combined in a compact 32 QFN package. An internal
LVDSOutputOptions high bandwidth sample and hold and a low jitter clock
• SupportsSine,LVCMOS,LVPECL, LVDSClock buffer help to achieve high SNR and high SFDR even
Inputs,andClockAmplitudeDownto400 athigh input frequencies.
mVPP The ADS614X feature coarse and fine gain options to
• ClockDutyCycleStabilizer improve SFDR performance at lower full-scale analog
• InternalReferencewithSupportforExternal input ranges.
Reference The digital data outputs are either parallel CMOS or
• NoExternal DecouplingRequiredfor DDR (Double Data Rate) LVDS. Several features
exist to ease data capture such as — controls for
References
output clock position and output buffer drive strength,
• ProgrammableOutputClock Positionand
LVDS current, and internal termination
DriveStrengthtoEaseData Capture programmability.
• 3.3-VAnalogand1.8-V to3.3-V DigitalSupply
The output interface type, gain, and other functions
• 32-QFNPackage(5mm· 5mm) are programmed using a 3-wire serial interface.
• PinCompatible12-BitFamily(ADS612X) Alternatively, some functions are configured using
dedicatedparallelpins sothedevice powersup to the
APPLICATIONS desiredstate.
• WirelessCommunicationsInfrastructure The ADS614X include internal references while
• SoftwareDefinedRadio eliminating traditional reference pins and associated
• PowerAmplifierLinearization external decoupling. External reference mode is also
supported.
• 802.16d/e
• TestandMeasurementInstrumentation The ADS614X are specified over the industrial
temperaturerange(–40(cid:176) Cto85(cid:176) C).
• HighDefinition Video
• MedicalImaging
ADS614XPerformanceSummary
ADS6145 ADS6144 ADS6143 ADS6142
F =10MHz(0dBgain) 90 91 93 95
in
SFDR,dBc
F =170MHz(3.5dBgain) 78 82 83 84
in
F =10MHz(0dBgain) 73.7 74.1 74.5 74.6
in
SINAD,dBFS
F =170MHz(3.5dBgain) 68.6 70.5 70.6 71.5
in
Power,mW 417 374 318 285
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof
TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2007–2008,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
ADS6145, ADS6144
ADS6143, ADS6142
www.ti.com
SLWS198B–JULY2007–REVISEDMARCH2008
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore
susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
D D
D D D N
D N V G
V G R R
A A D D
CLKP CLOCK CLKOUTP
CLKM GEN CLKOUTM
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
INP Digital
14-Bit Encoder D6_D7_P
SHA
ADC and
D6_D7_M
INM Serializer
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
Control
VCM Reference
Interface D12_D13_P
D12_D13_M
ADS614X
LVDS MODE
T K N A N
E L E T D
S C S A P
E S D
R S
ADS61XXFAMILY
125MSPS 105MSPS 80MSPS 65MSPS
ADS614X
ADS6145 ADS6144 ADS6143 ADS6142
14Bits
ADS612X
ADS6125 ADS6124 ADS6123 ADS6122
12Bits
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PACKAGE/ORDERINGINFORMATION(1)
SPECIFIED
PACKAGE- PACKAGE PACKAGE ORDERING
PRODUCT TEMPERATURE TRANSPORTMEDIA
LEAD DESIGNATOR MARKING NUMBER
RANGE
ADS6145IRHBT TapeandReel,small
ADS6145 QFN-32(2) RHB –40(cid:176) Cto85(cid:176) C AZ6145
ADS6145IRHBR TapeandReel,large
ADS6144IRHBT TapeandReel,small
ADS6144 QFN-32(2) RHB –40(cid:176) Cto85(cid:176) C AZ6144
ADS6144IRHBR TapeandReel,large
ADS6143IRHBT TapeandReel,small
ADS6143 QFN-32(2) RHB –40(cid:176) Cto85(cid:176) C AZ6143
ADS6143IRHBR TapeandReel,large
ADS6142IRHBT TapeandReel,small
ADS6142 QFN-32(2) RHB –40(cid:176) Cto85(cid:176) C AZ6142
ADS6142IRHBR TapeandReel,large
(1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI
websiteatwww.ti.com.
(2) Forthermalpadsizeonthepackage,seethemechanicaldrawingsattheendofthisdatasheet.q =34(cid:176) C/W(0LFMairflow),
JA
q =30(cid:176) C/Wwhenusedwith2oz.coppertraceandpadsoldereddirectlytoaJEDECstandardfourlayer3in· 3in(7.62cm·
JC
7.62cm)PCB.
ABSOLUTE MAXIMUM RATINGS(1)
VALUE UNIT
Supplyvoltagerange,AVDD –0.3to3.9 V
V
I
Supplyvoltagerange,DRVDD –0.3to3.9 V
VoltagebetweenAGNDandDRGND –0.3to0.3 V
VoltagebetweenAVDDtoDRVDD –0.3to3.3 V
VoltageappliedtoVCMpin(inexternalreferencemode) –0.3to2 V
Voltageappliedtoanaloginputpins,INPandINM –0.3tominimum(3.6,AVDD+0.3) V
Voltageappliedtoanaloginputpins,CLKPandCLKM –0.3to(AVDD+0.3) V
T Operatingfree-airtemperaturerange –40to85 (cid:176) C
A
T Operatingjunctiontemperaturerange 125 (cid:176) C
J
T Storagetemperaturerange –65to150 (cid:176) C
stg
(1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings
only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating
conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
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RECOMMENDED OPERATING CONDITIONS
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
MIN NOM MAX UNIT
SUPPLIES
AVDD Analogsupplyvoltage 3 3.3 3.6 V
CMOSInterface 1.65 1.8to3.3 3.6 V
DRVDD Outputbuffersupplyvoltage(1)
LVDSInterface 3 3.3 3.6 V
ANALOGINPUTS
Differentialinputvoltagerange 2 V
pp
V Inputcommon-modevoltage 1.5±0.1 V
IC
VoltageappliedonVCMinexternalreferencemode 1.45 1.5 1.55 V
CLOCKINPUT
ADS6145 1 125
ADS6144 1 105
Inputclocksamplerate,F MSPS
S
ADS6143 1 80
ADS6142 1 65
Sinewave,ac-coupled 0.4 1.5
Inputclockamplitudedifferential LVPECL,ac-coupled ±0.8
V
(VCLKP–VCLKM) LVDS,ac-coupled ±0.35 pp
LVCMOS,ac-coupled 3.3
InputClockdutycycle 35% 50% 65%
DIGITALOUTPUTS
DEFAULT
ForC ≤5pFandDRVDD≥2.2V
LOAD strength
Outputbufferdrivestrength (2) ForC >5pFandDRVDD≥2.2V MAXIMUM
LOAD strength
MAXIMUM
ForDRVDD<2.2V
strength
CMOSInterface,maximumbufferstrength 10
Maximumexternalloadcapacitancefrom
C LVDSInterface,withoutinternaltermination 5 pF
LOAD eachoutputpintoDRGND
LVDSInterface,withinternaltermination 10
R Differentialloadresistance(external)betweentheLVDSoutputpairs 100 Ω
LOAD
T Operatingfree-airtemperature -40 85 (cid:176) C
A
(1) Foreasymigrationtonextgeneration,highersamplingspeeddevices(>125MSPS),use1.8VDRVDDsupply.
(2) SeeOutputBufferStrengthProgrammabilityintheapplicationsection.
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ELECTRICAL CHARACTERISTICS
Typicalvaluesareat25(cid:176) C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40(cid:176) CtoT =85(cid:176) C,AVDD=
MIN MAX
DRVDD=3.3V,maximumratedsamplingfrequency,50%clockdutycycle,–1dBFSdifferentialanaloginput,internal
referencemode,appliestoCMOSandLVDSinterfaces,unlessotherwisenoted.
ADS6145 ADS6144 ADS6143 ADS6142
PARAMETER FS=125MSPS FS=105MSPS FS=80MSPS FS=65MSPS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
RESOLUTION 14 14 14 14 Bits
ANALOGINPUT
Differentialinputvoltagerange 2 2 2 2 VPP
Differentialinputresistance(dc),
>1 >1 >1 >1 MΩ
seeFigure94
Differentialinputcapacitance,
7 7 7 7 pF
seeFigure95
Analoginputbandwidth 450 450 450 450 MHz
Analoginputcommon-modecurrent 180 151 114 92 m A
(perinputpinofeachADC)
REFERENCEVOLTAGES
VREFB Internalreferencebottomvoltage 1 1 1 1 V
VREFT Internalreferencetopvoltage 2 2 2 2 V
ΔVREF Internalreferenceerror -20 ±5 20 -20 ±5 20 -20 ±5 20 -20 ±5 20 mV
(VREFT–VREFB)
VCM Common-modeoutputvoltage 1.5 1.5 1.5 1.5 V
VCMOutputcurrentcapability 4 4 4 4 mA
DCACCURACY
Nomissingcodes Specified Specified Specified Specified
EO Offseterror -10 ±2 10 -10 ±2 10 -10 ±2 10 -10 ±2 10 mV
Offseterrortemperaturecoefficient 0.05 0.05 0.05 0.05 mV/(cid:176)C
Therearetwosourcesofgainerror–internalreferenceinaccuracyandchannelgainerror
EGREF Gainerrorduetointernalreference -1 0.25 1 -1 0.25 1 -1 0.25 1 -1 0.25 1 %FS
inaccuracyalone,(ΔVREF/2)%
EGCHAN Gainerrorofchannelalone(1) -1 ±0.3 1 -1 ±0.3 1 -1 ±0.3 1 -1 ±0.3 1 %FS
Channelgainerrortemperature 0.005 0.005 0.005 0.005 Δ%/(cid:176)C
coefficient
DNL Differentialnonlinearity -0.95 ±0.6 2 -0.95 ±0.6 2 -0.95 ±0.5 2 -0.95 ±0.5 2 LSB
INL Integralnonlinearity -4.5 ±2.5 4.5 -4.5 ±2.5 4.5 -4 ±2 4 -4 ±2 4 LSB
POWERSUPPLY
IAVDD Analogsupplycurrent 123 110 94 84 mA
Digitalsupplycurrent,CMOS
interface,
IDRVDD DRVDD=1.8V, 6.1 5.4 4.5 4.0 mA
Noloadcapacitance,Fin=2MHz(2)
Digitalsupplycurrent,LVDS
interface,
IDRVDD DRVDD=3.3V, 42 42 42 42 mA
with100-Ωexternaltermination
Totalpower,CMOS,
DRVDD=3.3V(3) 417 625 374 525 318 440 285 400 mW
Globalpowerdown 30 60 30 60 30 60 30 60 mW
(1) Specifiedbydesignandcharacterization;nottestedinproduction.
(2) InCMOSmode,theDRVDDcurrentscaleswiththesamplingfrequencyandtheloadcapacitanceontheoutputpins(seeFigure87).
(3) ThemaximumDRVDDcurrentdependsontheactualloadcapacitanceonthedigitaloutputlines.Notethatthemaximum
recommendedloadcapacitanceis10pF.
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ELECTRICAL CHARACTERISTICS
Typicalvaluesareat25(cid:176) C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40(cid:176) CtoT =85(cid:176) C,AVDD=
MIN MAX
DRVDD=3.3V,maximumratedsamplingfrequency,50%clockdutycycle,–1dBFSdifferentialanaloginput,internal
referencemode,appliestoCMOSandLVDSinterfaces,unlessotherwisenoted.
ADS6145 ADS6144 ADS6143 ADS6142
PARAMETER TESTCONDITIONS FS=125MSPS FS=105MSPS FS=80MSPS FS=65MSPS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
DYNAMICACCHARACTERISTICS
Fin=10MHz 73.9 74.3 74.6 74.7
Fin=50MHz 70 73.7 73.7 71 74.2 74.4
Fin=70MHz 73.3 70 73.9 74.1 71 74.4
SNR 0dBGain 71.1 71.8 72.3 72.7
Sraigtion,aCl-tMo-OnoSise Fin=170MHz 3.5dBCoarse 70.1 70.9 71.4 71.8 dBFS
gain
0dBGain 69.8 70.7 71.3 71.7
Fin=230MHz 3.5dBCoarse
69 69.9 70.4 70.9
gain
Fin=10MHz 74.5 74.4 74.9 75
Fin=50MHz 70.5 74.4 73.9 71.5 74.4 74.6
Fin=70MHz 74.1 70.5 74.1 74.3 71.5 74.6
SNR 0dBGain 72.3 72.3 72.8 72.9
Sraigtion,aLl-tVoD-nSoise Fin=170MHz 3.5dBCoarse 71.5 71.5 71.9 72.1 dBFS
gain
0dBGain 71.2 71.2 71.8 72
Fin=230MHz 3.5dBCoarse
70.5 70.5 71.1 71.2
gain
RMSoutput
Inputstiedtocommon-mode 1.05 1.05 1.05 1.05 LSB
noise
Fin=10MHz 73.7 74.1 74.5 74.6
Fin=50MHz 69 72.3 73 70 74.1 74.1
SINAD Fin=70MHz 72.6 69 73.2 73.3 70 74.0
Signal-to-noise 0dBGain 68.7 71 71.1 72.2
arantdiodistortion Fin=170MHz 3.5dBCoarse 68.6 70.5 70.6 71.5 dBFS
gain
CMOS
0dBGain 67.3 69 70.2 70.6
Fin=230MHz 3.5dBCoarse
67 69 69.9 70.4
gain
Fin=10MHz 74.3 74.3 74.8 74.9
Fin=50MHz 69.5 72.7 72.9 70.5 74.3 74.4
SINAD Fin=70MHz 73.4 69.5 73.5 73.6 70.5 74.4
Signal-to-noise 0dBGain 70.6 71.4 72 72.4
arantdiodistortion Fin=170MHz 3.5dBCoarse 70.8 71.1 71.6 71.9 dBFS
gain
LVDS
0dBGain 69.4 69.2 71 70.5
Fin=230MHz 3.5dBCoarse
69.4 69.4 70.7 70.5
gain
ENOB Fin=50MHz 11.1 11.7 11.3 12
Effective Bits
numberofbits Fin=70MHz 11.1 11.8 11.3 12
Fin=10MHz 90 91 93 95
Fin=50MHz 76 80 83 79 89 89
Fin=70MHz 84 78 84 84 79 86
SFDR 0dBGain 76 80 81 82
Sdypnuarimouicsrfarenege Fin=170MHz 3.5dBCoarse 78 82 83 84 dBc
gain
0dBGain 75 77 79 79
Fin=230MHz 3.5dBCoarse
76 79 81 82
gain
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ELECTRICAL CHARACTERISTICS (continued)
Typicalvaluesareat25(cid:176) C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40(cid:176) CtoT =85(cid:176) C,AVDD=
MIN MAX
DRVDD=3.3V,maximumratedsamplingfrequency,50%clockdutycycle,–1dBFSdifferentialanaloginput,internal
referencemode,appliestoCMOSandLVDSinterfaces,unlessotherwisenoted.
ADS6145 ADS6144 ADS6143 ADS6142
PARAMETER TESTCONDITIONS FS=125MSPS FS=105MSPS FS=80MSPS FS=65MSPS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
Fin=10MHz 88.5 90 91.5 93
Fin=50MHz 73 79.5 82.5 76 88 88
Fin=70MHz 82 75 83 83 76 85
THD 0dBGain 73.5 79 78 80
Tdiosttaolrthioanrmonic Fin=170MHz 3.5dBCoarse 75 81 79 82 dBc
gain
0dBGain 71.5 75.5 76 76
Fin=230MHz 3.5dBCoarse
72.5 77.5 78 78.5
gain
Fin=10MHz 96 96 97 98
Fin=50MHz 76 95 96 79 96 96
Fin=70MHz 91 78 92 93 79 93
HD2
0dBGain 81 83 83 86
Second
harmonic Fin=170MHz 3.5dBCoarse dBc
82 84 84 87
distortion gain
0dBGain 75 79 80 79
Fin=230MHz 3.5dBCoarse
76 81 81 81
gain
Fin=10MHz 90 91 93 95
Fin=50MHz 76 80 83 79 89 89
Fin=70MHz 84 78 84 84 79 86
HD3 0dBGain 76 80 81 82
Tdihsitrodrthioanrmonic Fin=170MHz 3.5dBCoarse 78 82 83 84 dBc
gain
0dBGain 75 77 79 79
Fin=230MHz 3.5dBCoarse
76 79 81 82
gain
Fin=10MHz 93 94 96 97
Worstspur Fin=50MHz 92 90 93 96
(otherthan Fin=70MHz 91 90 92 95 dBc
HD2,HD3)
Fin=170MHz 90 89 89 91
Fin=230MHz 90 88 89 90
IMD
2-Tone F1=185MHz,F2=190MHz,
83 82 84 88 dBFS
intermodulation Eachtoneat-7dBFS
distortion
Recoverytowithin1%(offinal
Inputoverload clock
value)for6-dBoverloadwithsine 1 1 1 1
recovery cycles
waveinput
PSRR
ACPower For100mVppsignalonAVDD
35 35 35 35 dBc
supplyrejection supply
ratio
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DIGITAL CHARACTERISTICS(1)
Thedcspecificationsrefertotheconditionwherethedigitaloutputsarenotswitching,butarepermanentlyatavalidlogic
level0or1,AVDD=3.3V
ADS6145/ADS6144
PARAMETER TESTCONDITIONS
ADS6143/ADS6142
MIN TYP MAX UNIT
DIGITALINPUTS
PDN,SCLK,SDATA,andSEN (2)
High-levelinputvoltage 2.4 V
Low-levelinputvoltage 0.8 V
High-levelinputcurrent 33 m A
Low-levelinputcurrent –33 m A
Inputcapacitance 4 pF
DIGITALOUTPUTS
CMOSINTERFACE,DRVDD=1.8to3.3V
High-leveloutputvoltage DRVDD V
Low-leveloutputvoltage 0 V
Outputcapacitanceinsidethedevice,from
Outputcapacitance 2 pF
eachoutputtoground
DIGITALOUTPUTS
LVDSINTERFACE,DRVDD=3.3V,I =3.5mA,R =100Ω (3)
O L
High-leveloutputvoltage 1375 mV
Low-leveloutputvoltage 1025 mV
|V | Outputdifferentialvoltage 225 350 mV
OD
V Outputoffsetvoltage,single-ended Common-modevoltageofOUTP,OUTM 1200 mV
OS
Outputcapacitanceinsidethedevice,from
Outputcapacitance 2 pF
eitheroutputtoground
(1) AllLVDSandCMOSspecificationsarecharacterized,butnottestedatproduction.
(2) SCLKandSENfunctionasdigitalinputpinswhentheyareusedforserialinterfaceprogramming.Whenusedasparallelcontrolpins,
analogvoltageneedstobeappliedasperTable1&Table2
(3) I ReferstotheLVDSbuffercurrentsetting,R isthedifferentialloadresistancebetweentheLVDSoutputpair.
O L
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TIMING CHARACTERISTICS – LVDS AND CMOS MODES(1)
Typicalvaluesareat25(cid:176) C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40(cid:176) CtoT =85(cid:176) C,AVDD=
MIN MAX
DRVDD=3.3V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V clockamplitude,C =5pF(2),I =3.5
PP L O
mA,R =100Ω (3),nointernaltermination,unlessotherwisenoted.
L
Fortimingsatlowersamplingfrequencies,seesectionOutputTimingsintheAPPLICATIONINFORMATIONofthisdata
sheet.
ADS6145 ADS6144 ADS6143 ADS6142
PARAMETER TESTCONDITIONS FS=125MSPS FS=105MSPS FS=80MSPS FS=65MSPS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
Aperture
ta delay 0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 ns
Aperture
tj jitter 150 150 150 150 fsrms
Fromglobalpower 15 50 15 50 15 50 15 50 m s
down
Wake-up
time Fromstandby 15 50 15 50 15 50 15 50 m s
(tovalid
Fromoutput CMOS 100 200 100 200 100 200 100 200 ns
data)
buffer
disable LVDS 200 500 200 500 200 500 200 500 ns
clock
Latency 9 9 9 9
cycles
DDRLVDSMODE(4),DRVDD=3.3V
Datavalid(6)to
Datasetup
tsu time(5) zero-crossof 1.7 2.3 2.5 3.1 3.9 4.5 5.4 6.0 ns
CLKOUTP
Zero-crossof
Datahold
th time(5) CbeLcKoOmUinTgPintovadliadt(a6) 0.7 1.7 0.7 1.7 0.7 1.7 0.7 1.7 ns
Inputclockrisingedge
Clock
zero-crosstooutput
tPDI propagation clockrisingedge 4.3 5.8 7.3 4.3 5.8 7.3 4.3 5.8 7.3 4.3 5.8 7.3 ns
delay
zero-cross
Dutycycleof
LVDSbit differentialclock,
clockduty (CLKOUTP- 40% 47% 55% 40% 47% 55% 40% 47% 55% 40% 47% 55%
cycle CLKOUTM),
10≤Fs≤125MSPS
Risetimemeasured
from–50mVto50
Datarise
mV,
tr time, Falltimemeasured 70 100 170 70 100 170 70 100 170 70 100 170 ps
tf Datafall from50mVto–50
time
mV,
1≤Fs≤125MSPS
Risetimemeasured
from–50mVto50
tCLKRI Outputclock mV,
SE risetime, Falltimemeasured 70 100 170 70 100 170 70 100 170 70 100 170 ps
tCLKFA Outputclock from50mVto–50
LL falltime mV,
1≤Fs≤125MSPS
PARALLELCMOSMODE,DRVDD=2.5Vto3.3V,defaultoutputbufferdrivestrength(7)
Datasetup Datavalid(8)to50%of
tsu time(5) CLKOUTrisingedge 2.9 4.4 3.6 5.1 5.1 6.6 6.5 8.0 ns
50%ofCLKOUTrising
Datahold
th time(5) eindvgaelidto(8)databecoming 1.3 2.7 2.1 3.5 3.6 5.0 5.1 6.5 ns
(1) Timingparametersarespecifiedbydesignandcharacterizationandnottestedinproduction.
(2) C istheEffectiveexternalsingle-endedloadcapacitancebetweeneachoutputpinandground.
L
(3) I ReferstotheLVDSbuffercurrentsetting;R isthedifferentialloadresistancebetweentheLVDSoutputpair.
O L
(4) Measurementsaredonewithatransmissionlineof100Ωcharacteristicimpedancebetweenthedeviceandtheload.
(5) Setupandholdtimespecificationstakeintoaccounttheeffectofjitterontheoutputdataandclock.
(6) Datavalidreferstoalogichighof+100mVandlogiclowof–100mV.
(7) ForDRVDD<2.2V,itisrecommendedtouseanexternalclockfordatacaptureandNOTthedeviceoutputclocksignal(CLKOUT).
SeeParallelCMOSinterfaceintheapplicationsection.
(8) Datavalidreferstoalogichighof2V(1.7V)andlogiclowof0.8V(0.7V)forDRVDD=3.3V(2.5V).
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TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)
Fortimingsatlowersamplingfrequencies,seesectionOutputTimingsintheAPPLICATIONINFORMATIONofthisdata
sheet.
ADS6145 ADS6144 ADS6143 ADS6142
PARAMETER TESTCONDITIONS FS=125MSPS FS=105MSPS FS=80MSPS FS=65MSPS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
Clock Inputclockrisingedge
tPDI propagation zero-crossto50%of 5 6.5 7.9 5 6.5 7.9 5 6.5 7.9 5 6.5 7.9 ns
delay CLKOUTrisingedge
Dutycycleofoutput
Outputclock
clock(CLKOUT), 45% 50% 55% 45% 50% 55% 45% 50% 55% 45% 50% 55%
dutycycle
10≤Fs≤125MSPS
Risetimemeasured
from20%to80%of
Datarise
DRVDD,
tr time, Falltimemeasured 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 ns
tf Datafall from80%to20%of
time
DRVDD,
1≤Fs≤125MSPS
Risetimemeasured
from20%to80%of
tCLKRI Outputclock DRVDD,
SE risetime, Falltimemeasured 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 ns
tCLKFA Outputclock from80%to20%of
LL falltime DRVDD,
1≤Fs≤125MSPS
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