128/256 kB ISP/IAP flash with 10-bit ADC

42 Pages·2011·0.28 MB·English

LPC2114/2124
Single-chip 16/32-bit microcontrollers; 128/256 kB ISP/IAP
flash with 10-bit ADC
Rev. 7 — 10 June 2011 Product data sheet
1. General description
The LPC2114/2124 are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation
and embedded trace support, together with 128/256 kB of embedded high-speed flash
memory. A 128-bit wide memory interface and a unique accelerator architecture enable
32-bit code execution at maximum clock rate. For critical code size applications, the
alternative 16-bit Thumb mode reduces code by more than 30% with minimal
performance penalty.
With their compact 64-pin package, low power consumption, various 32-bit timers,
4-channel 10-bit ADC, PWM channels and 46 fast GPIO lines with up to nine external
interrupt pins these microcontrollers are particularly suitable for industrial control, medical
systems, access control and point-of-sale. With a wide range of serial communications
interfaces, they are also very well suited for communication gateways, protocol converters
and embedded soft modems as well as many other general-purpose applications.
Remark: Throughout the data sheet, the term LPC2114/2124 will apply to devices with
and without the /00 or /01 suffixes. The /00 or the /01 suffix will be used to differentiate
from other devices only when necessary.
2. Features and benefits
2.1 Key features brought by LPC2114/2124/01 devices
 Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original device.
They also allow for a port pin to be read at any time regardless of its function.
 Dedicated result registers for ADC(s) reduce interrupt overhead. The ADC pads are
5V tolerant when configured for digital I/O function(s).
 UART0/1 include fractional baud rate generator, auto-bauding capabilities and
handshake flow-control fully implemented in hardware.
 Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.
 SPI programmable data length and master mode enhancement.
 Diversified Code Read Protection (CRP) enables different security levels to be
implemented. This feature is available in LPC2114/2124/00 devices as well.
 General purpose timers can operate as external event counters.
2.2 Key features common for all devices
 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
 16kB on-chip static RAM.
LPC2114/2124
NXP Semiconductors
Single-chip 16/32-bit microcontrollers
 128/256kB on-chip flash program memory. 128-bit wide interface/accelerator enables
high speed 60 MHz operation.
 In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software. Flash programming takes 1ms per 512 B line. Single sector or
full chip erase takes 400ms.
 EmbeddedICE-RT interface enables breakpoints and watch points. Interrupt service
routines can continue to execute whilst the foreground task is debugged with the
on-chip RealMonitor software.
 Embedded Trace Macrocell (ETM) enables non-intrusive high speed real-time tracing
of instruction execution.
 Four-channel 10-bit ADC with conversion time as low as 2.44s.
 Two 32-bit timers (with four capture and four compare channels), PWM unit (six
outputs), Real-Time Clock (RTC) and watchdog.
 Multiple serial interfaces including two UARTs (16C550), Fast I2C-bus (400 kbit/s) and
two SPIs.
 60MHz maximum CPU clock available from programmable on-chip Phase-Locked
Loop with settling time of 100s.
 Vectored Interrupt Controller with configurable priorities and vector addresses.
 Up to forty-six 5V tolerant general purpose I/O pins. Up to nine edge or level sensitive
external interrupt pins available.
 On-chip crystal oscillator with an operating range of 1MHz to 30MHz.
 Two low power modes, Idle and Power-down.
 Processor wake-up from Power-down mode via external interrupt.
 Individual enable/disable of peripheral functions for power optimization.
 Dual power supply:
CPU operating voltage range of 1.65V to 1.95V (1.8V 0.15V).
I/O power supply range of 3.0 V to 3.6 V (3.3 V 10%) with 5V tolerant I/O pads.
16/32-bit ARM7TDMI-S processor.
3. Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
LPC2114FBD64/01 LQFP64 plastic low profile quad flat package; 64 leads; SOT314-2
body 10101.4mm
LPC2124FBD64/01 LQFP64 plastic low profile quad flat package; 64 leads; SOT314-2
body 10101.4mm
LPC2114_2124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 10 June 2011 2 of 42
LPC2114/2124
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Single-chip 16/32-bit microcontrollers
3.1 Ordering options
Table 2. Ordering options
Type number Flash RAM Fast GPIO/SSP/ Temperature range
memory Enhanced
UART, ADC,
Timer
LPC2114FBD64/01 128kB 16kB yes 40C to +85 C
LPC2124FBD64/01 256kB 16kB yes 40C to +85 C
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Product data sheet Rev. 7 — 10 June 2011 3 of 42
LPC2114/2124
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Single-chip 16/32-bit microcontrollers
4. Block diagram

TMS(2) TDI(2) RTCK(2) XTAL2
TRST(2) TCK(2) TDO(2) XTAL1 RESET
LPC2114 TEST/DEBUG E
LPC2124 INTERFACE ON DUL PLL SYSTEM
ATIMO FUNCTIONS
P0[30:27], HIGH-SPEED ARM7TDMI-S ULE
P0[25:0] 46 PGINPSIO T(3O)TAL EMRAC scylsotcekm VECTORED
P1[31:16] AHB BRIDGE T INTERRUPT
CONTROLLER
ARM7 LOCAL BUS AMBA Advanced High-performance
Bus (AHB)
INTERNAL
MEMORY
SRAM
ACCELERATOR
CONTROLLER AHB
DECODER
16 kB 128/256 kB AHB TO APB APB
SRAM FLASH BRIDGE DIVIDER
SCL(1)
I2C-BUS SERIAL
INTERFACE
EINT[3:0](1) EXTERNAL SDA(1)
INTERRUPTS
SCK0(1)
4 × CAP0(1) CAPTURE/ SPI0 MOSI0(1)
4 × CAP1(1) COMPARE SERIAL INTERFACE MISO0(1)
4 × MAT0(1) TIMER 0/TIMER 1 SSEL0(1)
4 × MAT1(1)
SCK1(1)
AIN[3:0](1) A/D CONVERTER SPI1/SSP(3) MOSI1(1)
SERIAL INTERFACE MISO1(1)
SSEL1(1)
P0[30:27], TXD[1:0](1)
P0[25:0] PUGREPNOESREA LI/O UART0/UART1 RXD[1:0](1)
P1[31:16] DSR1(1), CTS1(1),
RTS1(1), DTR1(1),
DCD1(1), RI1(1)
PWM[6:1](1) PWM0 WATCHDOG
TIMER
SYSTEM
REAL-TIME CLOCK
CONTROL
002aad175
(1) Shared with GPIO.
(2) When test/debug interface is used, GPIO/other functions sharing these pins are not available.
(3) SSP interface and high-speed GPIO are available on LPC2114/01 and LPC2124/01 only.
Fig 1. Block diagram
LPC2114_2124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 10 June 2011 4 of 42
LPC2114/2124
NXP Semiconductors
Single-chip 16/32-bit microcontrollers
5. Pinning information
5.1 Pinning

2] 3]
NT3 AP1[ AT1[
EI C M
1/ 1/ 1/
SSEL MOSI MISO
3]/ 2]/ 3]/
1[ 1[ 1[
1[27]/TDO DDA(1V8) TAL1 TAL2 1[28]/TDI SSA SSA(PLL) ESET 1[29]/TCK 0[20]/MAT 0[19]/MAT 0[18]/CAP 1[30]/TMS DD(3V3) SS DD(1V8)
P V X X P V V R P P P P P V V V
4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9
6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4
P0[21]/PWM5/CAP1[3] 1 48 P1[20]/TRACESYNC
P0[22]/CAP0[0]/MAT0[0] 2 47 P0[17]/CAP1[2]/SCK1/MAT1[2]
P0[23] 3 46 P0[16]/EINT0/MAT0[2]/CAP0[2]
P1[19]/TRACEPKT3 4 45 P0[15]/RI1/EINT2
P0[24] 5 44 P1[21]/PIPESTAT0
VSS 6 43 VDD(3V3)
VDDA(3V3) 7 42 VSS
P1[18]/TRACEPKT2 8 LPC2114 41 P0[14]/DCD1/EINT1
P0[25] 9 LPC2124(1) 40 P1[22]/PIPESTAT1
n.c. 10 39 P0[13]/DTR1/MAT1[1]
P0[27]/AIN0/CAP0[1]/MAT0[1] 11 38 P0[12]/DSR1/MAT1[0]
P1[17]/TRACEPKT1 12 37 P0[11]/CTS1/CAP1[1]
P0[28]/AIN1/CAP0[2]/MAT0[2] 13 36 P1[23]/PIPESTAT2
P0[29]/AIN2/CAP0[3]/MAT0[3] 14 35 P0[10]/RTS1/CAP1[0]
P0[30]/AIN3/EINT3/CAP0[0] 15 34 P0[9]/RXD1/PWM6/EINT3
P1[16]/TRACEPKT0 16 33 P0[8]/TXD1/PWM4
7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2
1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 002aad176
VDD(1V8) VSS P0[0]/TXD0/PWM1 P1[31]/TRST P0[1]/RXD0/PWM3/EINT0 P0[2]/SCL/CAP0[0] VDD(3V3) P1[26]/RTCK VSS P0[3]/SDA/MAT0[0]/EINT1 P0[4]/SCK0/CAP0[1] P1[25]/EXTIN0 P0[5]/MISO0/MAT0[1] P0[6]/MOSI0/CAP0[2] P0[7]/SSEL0/PWM2/EINT2 P1[24]/TRACECLK
(1) Pin configuration is identical for devices with and without the /00 and /01 suffixes.
Fig 2. Pin configuration
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Product data sheet Rev. 7 — 10 June 2011 5 of 42
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Single-chip 16/32-bit microcontrollers
5.2 Pin description
Table 3. Pin descripti on
Symbol Pin Type Description
P0[0] to P0[31] I/O Port 0 is a 32-bit bidirectional I/O port with individual direction controls for each bit.
The operation of port 0 pins depends upon the pin function selected via the Pin
Connect Block. Pins 26 and 31 of port 0 are not available.
P0[0]/TXD0/ 19 O TXD0 — Transmitter output for UART0.
PWM1
O PWM1 — Pulse Width Modulator output 1.
P0[1]/RXD0/ 21 I RXD0 — Receiver input for UART0.
PWM3/EINT0
O PWM3 — Pulse Width Modulator output 3.
I EINT0 — External interrupt 0 input
P0[2]/SCL/ 22 I/O SCL — I2C-bus clock input/output. Open-drain output (for I2C-bus compliance).
CAP0[0]
I CAP0[0] — Capture input for Timer0, channel 0.
P0[3]/SDA/ 26 I/O SDA — I2C-bus data input/output. Open-drain output (for I2C-bus compliance).
MAT0[0]/EINT1
O MAT0[0] — Match output for Timer0, channel 0.
I EINT1 — External interrupt 1 input.
P0[4]/SCK0/ 27 I/O SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.
CAP0[1]
I CAP0[1] — Capture input for Timer0, channel 1.
P0[5]/MISO0/ 29 I/O MISO0 — Master In Slave OUT for SPI0. Data input to SPI master or data output
MAT0[1] from SPI slave.
O MAT0[1] — Match output for Timer0, channel 1.
P0[6]/MOSI0/ 30 I/O MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data input
CAP0[2] to SPI slave.
I CAP0[2] — Capture input for Timer0, channel 2.
P0[7]/SSEL0/ 31 I SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.
PWM2/EINT2
O PWM2 — Pulse Width Modulator output 2.
I EINT2 — External interrupt 2 input.
P0[8]/TXD1/ 33 O TXD1 — Transmitter output for UART1.
PWM4
O PWM4 — Pulse Width Modulator output 4.
P0[9]/RXD1/ 34 I RXD1 — Receiver input for UART1.
PWM6/EINT3
O PWM6 — Pulse Width Modulator output 6.
I EINT3 — External interrupt 3 input.
P0[10]/RTS1/ 35 O RTS1 — Request to Send output for UART1.
CAP1[0]
I CAP1[0] — Capture input for Timer1, channel 0.
P0[11]/CTS1/ 37 I CTS1 — Clear to Send input for UART1.
CAP1[1]
I CAP1[1] — Capture input for Timer1, channel 1.
P0[12]/DSR1/ 38 I DSR1 — Data Set Ready input for UART1.
MAT1[0]
O MAT1[0] — Match output for Timer1, channel 0.
P0[13]/DTR1/ 39 O DTR1 — Data Terminal Ready output for UART1.
MAT1[1]
O MAT1[1] — Match output for Timer1, channel 1.
P0[14]/DCD1/ 41 I DCD1 — Data Carrier Detect input for UART1.
EINT1
I EINT1 — External interrupt 1 input.
Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take
control of the part after reset.
LPC2114_2124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 10 June 2011 6 of 42
LPC2114/2124
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Single-chip 16/32-bit microcontrollers
Table 3. Pin description …continued
Symbol Pin Type Description
P0[15]/RI1/EINT2 45 I RI1 — Ring Indicator input for UART1.
I EINT2 — External interrupt 2 input.
P0[16]/EINT0/ 46 I EINT0 — External interrupt 0 input.
MAT0[2]/CAP0[2]
O MAT0[2] — Match output for Timer0, channel 2.
I CAP0[2] — Capture input for Timer0, channel 2.
P0[17]/CAP1[2]/ 47 I CAP1[2] — Capture input for Timer1, channel 2.
SCK1/MAT1[2]
I/O SCK1 — Serial Clock for SPI1/SSP[1]. SPI clock output from master or input to
slave.
O MAT1[2] — Match output for Timer1, channel 2.
P0[18]/CAP1[3]/ 53 I CAP1[3] — Capture input for Timer1, channel 3.
MISO1/MAT1[3]
I/O MISO1 — Master In Slave Out for SPI1/SSP[1]. Data input to SPI master or data
output from SPI slave.
O MAT1[3] — Match output for Timer1, channel 3.
P0[19]/MAT1[2]/ 54 O MAT1[2] — Match output for Timer1, channel 2.
MOSI1/CAP1[2]
I/O MOSI1 — Master Out Slave In for SPI1/SSP[1]. Data output from SPI master or data
input to SPI slave.
I CAP1[2] — Capture input for Timer1, channel 2.
P0[20]/MAT1[3]/ 55 O MAT1[3] — Match output for Timer1, channel 3.
SSEL1/EINT3
I SSEL1 — Slave Select for SPI1/SSP[1]. Selects the SPI interface as a slave.
I EINT3 — External interrupt 3 input.
P0[21]/PWM5/ 1 O PWM5 — Pulse Width Modulator output 5.
CAP1[3]
I CAP1[3] — Capture input for Timer1, channel 3.
P0[22]/CAP0[0]/ 2 I CAP0[0] — Capture input for Timer0, channel 0.
MAT0[0]
O MAT0[0] — Match output for Timer0, channel 0.
P0[23] 3 I/O general purpose bidirectional digital port only
P0[24] 5 I/O general purpose bidirectional digital port only
P0[25] 9 I/O general purpose bidirectional digital port only
P0[27]/AIN0/ 11 I AIN0 — ADC, input 0. This analog input is always connected to its pin.
CAP0[1]/MAT0[1]
I CAP0[1] — Capture input for Timer0, channel 1.
O MAT0[1] — Match output for Timer0, channel 1.
P0[28]/AIN1/ 13 I AIN1 — ADC, input 1. This analog input is always connected to its pin.
CAP0[2]/MAT0[2]
I CAP0[2] — Capture input for Timer0, channel 2.
O MAT0[2] — Match output for Timer0, channel 2.
P0[29]/AIN2/ 14 I AIN2 — ADC, input 2. This analog input is always connected to its pin.
CAP0[3]/MAT0[3]
I CAP0[3] — Capture input for Timer0, Channel 3.
O MAT0[3] — Match output for Timer0, channel 3.
P0[30]/AIN3/ 15 I AIN3 — ADC, input 3. This analog input is always connected to its pin.
EINT3/CAP0[0]
I EINT3 — External interrupt 3 input.
I CAP0[0] — Capture input for Timer0, channel 0.
P1[0] to P1[31] I/O Port 1 is a 32-bit bidirectional I/O port with individual direction controls for each bit.
The operation of port 1 pins depends upon the pin function selected via the Pin
Connect Block. Pins 0 through 15 of port1 are not available.
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Product data sheet Rev. 7 — 10 June 2011 7 of 42
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Single-chip 16/32-bit microcontrollers
Table 3. Pin description …continued
Symbol Pin Type Description
P1[16]/ 16 O Trace Packet, bit 0. Standard I/O port with internal pull-up.
TRACEPKT0
P1[17]/ 12 O Trace Packet, bit 1. Standard I/O port with internal pull-up.
TRACEPKT1
P1[18]/ 8 O Trace Packet, bit 2. Standard I/O port with internal pull-up.
TRACEPKT2
P1[19]/ 4 O Trace Packet, bit 3. Standard I/O port with internal pull-up.
TRACEPKT3
P1[20]/ 48 O Trace Synchronization. Standard I/O port with internal pull-up.
TRACESYNC Note: LOW on this pin while RESET is LOW, enables pins P1[25:16] to operate as
Trace port after reset.
P1[21]/ 44 O Pipeline Status, bit 0. Standard I/O port with internal pull-up.
PIPESTAT0
P1[22]/ 40 O Pipeline Status, bit 1. Standard I/O port with internal pull-up.
PIPESTAT1
P1[23]/ 36 O Pipeline Status, bit 2. Standard I/O port with internal pull-up.
PIPESTAT2
P1[24]/ 32 O Trace Clock. Standard I/O port with internal pull-up.
TRACECLK
P1[25]/EXTIN0 28 I External Trigger Input. Standard I/O with internal pull-up.
P1[26]/RTCK 24 I/O Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger
synchronization when processor frequency varies. Bidirectional pin with internal
pull-up.
Note: LOW on this pin while RESET is LOW, enables pins P1[31:26] to operate as
Debug port after reset.
P1[27]/TDO 64 O Test Data out for JTAG interface.
P1[28]/TDI 60 I Test Data in for JTAG interface.
P1[29]/TCK 56 I Test Clock for JTAG interface. This clock must be slower than 1⁄ of the CPU clock
6
(CCLK) for the JTAG interface to operate.
P1[30]/TMS 52 I Test Mode Select for JTAG interface.
P1[31]/TRST 20 I Test Reset for JTAG interface.
n.c. 10 pin not connected.
RESET 57 I external reset input; a LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor execution to begin at
address 0. TTL with hysteresis, 5V tolerant.
XTAL1 62 I input to the oscillator circuit and internal clock generator circuits.
XTAL2 61 O output from the oscillator amplifier.
V 6, 18, 25, I ground: 0V reference.
SS
42, 50
V 59 I analog ground; 0V reference. This should nominally be the same voltage as V ,
SSA SS
but should be isolated to minimize noise and error.
V 58 I PLL analog ground; 0V reference. This should nominally be the same voltage as
SSA(PLL)
V , but should be isolated to minimize noise and error.
SS
V 17, 49 I 1.8V core power supply; this is the power supply voltage for internal circuitry.
DD(1V8)
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Product data sheet Rev. 7 — 10 June 2011 8 of 42
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Single-chip 16/32-bit microcontrollers
Table 3. Pin description …continued
Symbol Pin Type Description
V 63 I analog 1.8V core power supply; this is the power supply voltage for internal
DDA(1V8)
circuitry. This should be nominally the same voltage as V but should be
DD(1V8)
isolated to minimize noise and error.
V 23, 43, 51 I 3.3V pad power supply; this is the power supply voltage for the I/O ports
DD(3V3)
V 7 I analog 3.3V pad power supply; this should be nominally the same voltage as
DDA(3V3)
V but should be isolated to minimize noise and error
DD(3V3)
[1] SSP interface available on LPC2114/01 and LPC2124/01 only.
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Product data sheet Rev. 7 — 10 June 2011 9 of 42
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Single-chip 16/32-bit microcontrollers
6. Functional description
Details of the LPC2114/2124 systems and peripheral functions are described in the
following sections.
6.1 Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
• The standard 32-bit ARM set.
• A 16-bit Thumb set.
The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65% of the code size of ARM, and 160% of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
6.2 On-chip flash program memory
The LPC2114/2124 incorporate a 128kB and 256kB flash memory system respectively.
This memory may be used for both code and data storage. Programming of the flash
memory may be accomplished in several ways. It may be programmed In System via the
serial port. The application program may also erase and/or program the flash while the
application is running, allowing a great degree of flexibility for data storage field firmware
upgrades, etc. When on-chip bootloader is used, 120kB and 248kB of flash memory is
available for user code.
The LPC2114/2124 flash memory provides a minimum of 100000 erase/write cycles and
20 years of data retention.
On-chip bootloader (as of revision 1.60) provides Code Read Protection (CRP) for the
LPC2114/2124 on-chip flash memory. When the CRP is enabled, the JTAG debug port
and ISP commands accessing either the on-chip RAM or flash memory are disabled.
LPC2114_2124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 10 June 2011 10 of 42