12-Bit ADC, MUX, PGA and Internal Reference - Texas Instruments

44 Pages·2014·0.87 MB·English

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SBAS124C − DECEMBER 1999 − REVISED DECEMBER 2005
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FEATURES DESCRIPTION
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PGA Gains: 1, 2, 4, 5, 8, 10, 16, 20 V/V The ADS7870 (US patents 6140872, 6060874) is a
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Programmable Input (Up to 4-Channel complete low-power data acquisition system on a single
Differential/Up to 8-Channel Single-Ended or chip. It consists of a 4-channel differential/8-channel
Some Combination) single-ended multiplexer, precision programmable gain
(cid:1) amplifier, 12-bit successive approximation analog-to-
1.15-V, 2.048-V, or 2.5-V Internal Reference
digital (A/D) converter, and a precision voltage reference.
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SPI/DSP Compatible Serial Interface
(≤20MHz) The programmable-gain amplifier provides high input
(cid:1) impedance, excellent gain accuracy, good common-mode
Throughput Rate: 52 kSamples/sec
rejection, and low noise.
(cid:1)
Error Overload Indicator
(cid:1) For many low-level signals, no external amplification or
Programmable Output 2s Complement/Binary
impedance buffering is needed between the signal source
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2.7-V to 5.5-V Single Supply Operation
and the A/D input.
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4-Bit Digital I/O Via Serial Interface
The offset voltage of the PGA is auto-zeroed. Gains of 1,
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Pin-Compatible With ADS7871 2, 4, 5, 8, 10, 16, and 20 V/V allow signals as low as 125
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SSOP-28 Package mV to produce full-scale digital outputs.
The ADS7870 contains an internal reference, which is
APPLICATIONS trimmed for high initial accuracy and stability vs
temperature. Drift is typically 10 ppm/°C. An external
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Portable Battery-Powered Systems
reference can be used in situations where multiple
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Low-Power Instrumentation ADS7870s share a common reference.
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Low-Power Control Systems The serial interface allows the use of SPI, QSPI,
(cid:1) Smart Sensor Applications Microwire, and 8051-family protocols, without glue logic.
BUFIN BUFOUT/REFIN
VREF REF
CCLK
Oscillator
LN0
OSC ENABLE
LN1
LN2
LN3 + 12-BIT BUSY
LN4 MUX P_GA A/D CONVERT
LN5
RESET
LN6
LN7 RISE/FALL
CS
Serial SCLK
I/O0
I/O1 Digital Registers Interface DIN
I/O2 I/O DOUT
I/O3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
QSPI and SPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
All other trademarks are the property of their respective owners.
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+%#$%&’ )% *.-+"$"+()"%#* .-& )3- )-&’* %$ (cid:12)-4(* (cid:11)#*)&,’-#)* *)(#1(&1 5(&&(#)62
(cid:16)&%1,+)"%# .&%+-**"#7 1%-* #%) #-+-**(&"06 "#+0,1- )-*)"#7 %$ (00 .(&(’-)-&*2
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SBAS124C − DECEMBER 1999 − REVISED DECEMBER 2005
ORDERING INFORMATION(1)
SPECIFIED
PACKAGE PACKAGE ORDERING TRANSPORT MEDIA,
PRODUCT PACKAGE-LEAD TEMPERATURE
DESIGNATOR MARKING NUMBER QUANTITY
RANGE
ADS7870 ADS7870IDB Rails, 48
AADDSS77887700 SSSSOOPP--2288 SSuurrffaaccee MMoouunntt DDBB −−4400°°CC ttoo ++8855°°CC
ADS7870 ADS7870IDBR Tape and Reel, 1000
(1)For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI web
site at www.ti.com.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
Supply voltage, VDD 5.5 V
Momentary 100 mA
IInnppuutt ccuurrrreenntt
AAnnaalloogg iinnppuuttss Continuous 10 mA
Input voltage VDD + 0.5 V to GND − 0.5 V
Operating free-air temperature range, TA −40°C to 85°C
Storage temperature range, TSTG −65°C to 150°C
Junction temperature (TJ max) 150°C
Lead temperature, soldering (10 sec) 300°C
(1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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SBAS124C − DECEMBER 1999 − REVISED DECEMBER 2005
ELECTRICAL CHARACTERISTICS
For the Total System (1), −40°C ≤ TA ≤ 85°C, VDD = 5 V, BUFIN = 2.5 V (using external reference), 2.5-MHz CCLK and 2.5-MHz SCLK (unless
otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Analog Input
Input voltage (LNx inputs) Linear operation −0.2 VDD + 0.2 V
Input capacitance (2) 4 to 9.7 pF
Common mode 6
IInnppuutt iimmppeeddaannccee ((22)) MMΩΩ
Differential 7
Channel-to-channel crosstalk VI = 2 VPP, 60 Hz (3) 100 dB
Maximum leakage current 100 pA
Static Accuracy
Resolution 12 Bits
No missing codes G = 1 to 20 V/V 12 Bits
Integral linearity G = 1 to 20 V/V −2.5 ±2 2.5 LSB
Differential linearity G = 1 to 20 V/V ±0.5 LSB
Offset error G = 1 to 20 V/V −6 ±1 6 LSB
RRaattiioommeettrriicc ccoonnffiigguurraattiioonn oorr G = 1 to 10 V/V −0.2 0.2 %FSR
external reference ((44)) G = 16 and 20 V/V −0.25 0.25 %FSR
FFuullll--ssccaallee ggaaiinn eerrrroorr
G = 1 to 10 V/V −0.35 0.35 %FSR
IInntteerrnnaall rreeffeerreennccee
G = 16 and 20 V/V −0.4 0.4 %FSR
DC common-mode rejection ratio, RTI VI = −0.2 V to 5.2 V, 92 dB
G = 20 V/V
Power supply rejection ratio, RTI VDD = 5 V ±10%, G = 20 V/V 86 dB
Dynamic Characteristics
Continuous mode One channel 52
TThhrroouugghhppuutt rraattee kkssaammppllee//ss
Address mode Different channels 52
External clock, CCLK (5) 0.1 20 MHz
Internal oscillator frequency 2.5 MHz
Serial interface clock, SCLK 20 MHz
Data setup time 10 ns
Data hold time 10 ns
Digital Inputs
Low-level input voltage, VIL 0.8 V
VDD ≤ 3.6 V 2 V
HHiigghh--lleevveell iinnppuutt vvoollttaaggee,, VVIIHH
LLooggiicc lleevveellss VDD >3.6 V 3 V
Low-level input current, IIL 1
µAA
High-level input current, IIH 1
(1)The specifications for the total system are overall analog input to digital output specifications. The specifications for internal functions indicate
the performance of the individual functions in the ADS7870.
(2)The ADS7870 uses switched capacitor techniques for the programmable gain amplifier and A/D converter. A characteristic of such circuits is that
the input capacitance at any selected LNx pin changes during the conversion cycle.
(3)One channel on with its inputs grounded. All other channels off with sinewave voltage applied to their inputs.
(4)Ratiometric configuration exists when the input source is configured such that changes in the reference cause corresponding changes in the input
voltage. The same accuracy applies when a perfect external reference is used.
(5)The CCLK is divided by the DF value specified by the contents of register 3, A/D Control register, bits D0 and D1 to produce DCLK. The maximum
value of DCLK is 2.5 MHz.
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SBAS124C − DECEMBER 1999 − REVISED DECEMBER 2005
ELECTRICAL CHARACTERISTICS
For the Total System (1), −40°C ≤ TA ≤ 85°C, VDD = 5 V, BUFIN = 2.5 V (using external reference), 2.5-MHz CCLK and 2.5-MHz SCLK (unless
otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Digital Outputs
Data coding Binary 2s complement
ISINK = 5 mA 0.4
LLooww--lleevveell oouuttppuutt vvoollttaaggee,, VVOOLL VV
ISINK = 16 mA 0.8
LLooggiicc lleevveellss
ISOURCE = 0.5 mA VDD − 0.4
HHiigghh--lleevveell oouuttppuutt vvoollttaaggee,, VVOOHH VV
ISOURCE = 5 mA 4.6
Leakage current Hi-Z state, VO = 0 V to VDD 1 µA
Output capacitance 5 pF
Voltage Reference
BBaannddggaapp vvoollttaaggee VREF = 2.048 V, 2.5 V Pin 26 used as output, −0.25 ±0.05 0.25 %FSR
UUssee iinntteerrnnaall OOSSCC oorr eexxtteerrnnaall
reference VREF = 1.15 V CCLK as conversion clock 1.15 V
Output drive ±0.6 µA
Reference Buffer
Input voltage, BUFIN 0.9 VDD − 0.2 V
Input impedance, BUFIN At pin 27 1000||3 GΩ||pF
Input offset −10 ±1 10 mV
OOuuttppuutt vvoollttaaggee aaccccuurraaccyy vvss tteemmppeerraattuurree,, PPiinn 2288 uusseedd aass oouuttppuutt,, −0.25 ±0.05 0.25 %FSR
BUFOUT/REFIN ((22)) ((33)) VREF = 2.048 V and 2.5 V 10 50 ppm/°C
Output drive, BUFOUT/REFIN 20 mA
Power Supply Requirements
Supply voltage 2.7 5.5 V
REF and BUF on, Internal os-
1-kHz Sample rate 0.45 mA
cillator on
REF and BUF on, External
Power supply current ((22)) 50-kHz Sample rate 1.2 1.7 mA
CCLK
REF, BUF, Internal
Power down 1 µA
oscillator off
REF and BUF on, Internal
1-kHz Sample rate 2.25 mW
oscillator on
Power dissipation ((22)) REF and BUF on, External
50-kHz Sample rate 6 8.5 mW
CCLK
Power down REF and BUF off 5 µW
Temperature Range
Operating free-air −40 85 °C
Storage range −65 150 °C
Thermal resistance, (cid:1)JA 65 °C/W
(1)The specifications for the total system are overall analog input to digital output specifications. The specifications for internal functions indicate
the performance of the individual functions in the ADS7870.
(2)REF and BUF contribute 190 µA and 150 µA (950 µW and 750 µW) respectively. At initial power up the default condition for both REF and BUF
functions is power off. They can be turned on under software control by writing a 1 to D3 and D2 of register 7, REF/OSCILLATOR CONTROL
register.
(3)For VDD < 3 V, VREF = 2.5 V is not usable.
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SBAS124C − DECEMBER 1999 − REVISED DECEMBER 2005
ELECTRICAL CHARACTERISTICS
For Internal Functions (1), −40°C ≤ TA ≤ 85°C, VDD = 5 V, BUFIN = 2.5 V (using external reference), 2.5-MHz CCLK and 2.5-MHz SCLK (unless
otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Multiplexer
On resistance 100 Ω
Off resistance 1 GΩ
On channel = 5.2 V,
Off channel = 0 V VLNx = 5.2 V 100 pA
OOffff cchhaannnneell lleeaakkaaggee
current On channel = 0 V,
100 pA
Off channel = 5.2 V
On channel = 5.2 V,
100 pA
Off channel = 0 V
OOnn cchhaannnneell lleeaakkaaggee
current On channel = 0 V,
100 pA
Off channel = 5.2 V
PGA Amplifier
Input capacitance (2) 4 to 9.7 pF
Common mode 6 MΩ
IInnppuutt iimmppeeddaannccee ((22))
Differential 7 MΩ
Offset voltage 100 µV
Small signal bandwidth 5/Gain MHz
G = 1 0.3 µs
SSeettttlliinngg ttiimmee
G = 20 6.4 µs
Analog-To-Digital Converter DC Characteristics
Resolution 12 Bits
Integral linearity error ±0.5 LSB
Differential linearity error ±0.5 LSB
No missing codes 12 Bits
Offset error REFIN = 2.5 V ±0.5 LSB
Full-scale (gain) error ±0.02 %
Common mode rejection, RTI of A/D 80 dB
Power supply rejection, RTI of ADS7870 External reference, VDD = 5 V ±10% 60 dB
PGA Plus A/D Converter Sampling Dynamics fCCLK = 2.5 MHz, DF = 1
Throughput rate 48 CCLK cycles 52 kHz
Conversion time 12 CCLK cycles 4.8 µs
Acquisition time 28 CCLK cycles 9.6 µs
Auto zero time 8 CCLK cycles 3.2 µs
Aperture delay 36 CCLK cycles 12.8 µs
Small signal bandwidth 5 MHz
Step response 1 Complete Conversion Cycle
(1)The specifications for the total system are overall analog input to digital output specifications. The specifications for internal functions indicate
the performance of the individual functions in the ADS7870.
(2)The ADS7870 uses switched capacitor techniques for the programmable gain amplifier and A/D converter. A characteristic of such circuits is that
the input capacitance at any selected LNx pin changes during the conversion cycle.
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SBAS124C − DECEMBER 1999 − REVISED DECEMBER 2005
PIN ASSIGNMENTS
SSOP-28 PACKAGE
(TOP VIEW)
LN0 1 28 BUFOUT/REFIN
LN1 2 27 BUFIN
LN2 3 26 VREF
LN3 4 25 GND
LN4 5 24 VDD
LN5 6 23 CS
LN6 7 22 DOUT
LN7 8 21 DIN
RESET 9 20 SCLK
RISE/FALL 10 19 CCLK
I/O0 11 18 OSC ENABLE
I/O1 12 17 BUSY
I/O2 13 16 CONVERT
I/O3 14 15 NC
Terminal Functions
TERMINAL
NO. NAME I/O DESCRIPTION
1−8 LN0−LN7 AI MUX input lines 0−7
9 RESET DI Master reset, zeros all registers
10 RISE/FALL DI Sets the active edge for SCLK. 0 sets SCLK active on falling edge. 1 sets SCLK active on rising edge.
11−14 I/O0−I/O3 DIO Digital input or output signal
15 NC − No connection or internal function. It is recommended that this pin be tied to ground.
16 CONVERT DI 0 to 1 transition starts a conversion cycle.
17 BUSY DO 1 indicates converter is busy
18 OSC ENABLE DI 0 sets CCLK as an input, 1 sets CCLK as an output and turns the oscillator on.
19 CCLK DIO If OSC ENABLE = 1, then the internal oscillator is output to this pin. If OSC ENABLE = 0, then this is the input
pin for an external conversion clock.
20 SCLK DI Serial data input/output transfer clock. Active edge set by the RISE/FALL pin. If RISE/FALL is low, SCLK is
active on the falling edge.
21 DIN DIO Serial data input. In the 3-wire mode, this pin is used for serial data input. In the 2-wire mode, serial data
output appears on this pin as well as the DOUT pin.
22 DOUT DO Serial data output. This pin is driven when CS is low and is high impedance when CS is high. This pin
behaves the same in both 3-wire and 2-wire modes.
23 CS DI Chip select. When CS is low, the serial interface is enabled. When CS is high, the serial interface is disabled,
the DOUT pin is high impedance, and the DIN pin is an input. The CS pin only affects the operation of the
serial interface. It does not directly enable/disable the operation of the signal conversion process.
24 VDD − Power supply voltage, 2.7 V to 5.5 V
25 GND − Power supply ground
26 VREF AO 2.048-/2.5-V on-chip voltage reference
27 BUFIN AI Input to reference buffer amplifier
28 BUFOUT/REFIN AIO Output from reference buffer amplifier and reference input to ADC
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SBAS124C − DECEMBER 1999 − REVISED DECEMBER 2005
TYPICAL PERFORMANCE CURVES†
GAIN ERROR OUTPUT OFFSET ERROR
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
15 10
Gain = 20
8
10 Gain = 8
B
Gain = 20 LS 6 Gain = 1
B −
ror − LS 5 Gain = 1 Gain = 8 et Error 4
n Er Offs 2
Gai 0 ut
− utp
G O 0
E −
−5 O
E
−2
−10 −4
−60 −40 −20 0 20 40 60 80 100 120 140 −60 −40 −20 0 20 40 60 80 100 120 140
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C
Figure 1 Figure 2
VOLTAGE REFERENCE ERROR INTERNAL OSCILLATOR FREQUENCY
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
0.4 2.55
3 Sigma
3 Sigma
0.2 2.50
z
H
M
r − % 0 VREF cy − 2.45 Avg
o n
Err ue
nce −0.2 −3 Sigma Freq 2.40
e Refere −0.4 scillator 2.35 −3 Sigma
g O
Volta −0.6 rnal 2.30
e
nt
−0.8 I 2.25
VREF = 2.048 V or 2.5 V
−1 2.20
−60 −40 −20 0 20 40 60 80 100 120 140 −60 −40 −20 0 20 40 60 80 100 120 140
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C
Figure 3 Figure 4
†At TA= 25°C, VDD = 5 V, VREF = 2.5 V connected to BUFIN (using internal reference), 2.5 MHz CCLK, and 2.5 MHz SCLK (unless otherwise noted)
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SBAS124C − DECEMBER 1999 − REVISED DECEMBER 2005
OUTPUT OFFSET ERROR OUTPUT OFFSET ERROR
vs vs
COMMON-MODE VOLTAGE POWER SUPPLY VOLTAGE
2 8
50 Ksps, CCLK = 2.5 MHz,
1.5 7 Gain = 20 VREF = 2.048 V
Gain = 10
B 1 B 6
S Gain = 1 S
Error − L 0.5 Gain = 10 Error − L 45
Output Offset −0−.015 Gain = 20 Output Offset 32 Gain = 1
− O 1 LSB = − 1
E −72 dB for Gain = 1, EO 4 LSB =
−1.5
−98 dB for Gain = 20 86 dB for Gain = 20,
0
60 dB for Gain = 1
−2 −1
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 2 2.5 3 3.5 4 4.5 5 5.5 6
Common-Mode Voltage − V VDD − Supply Voltage − V
Figure 5 Figure 6
QUIESCENT CURRENT PEAK-TO-PEAK OUTPUT NOISE
vs vs
SAMPLING RATE GAIN
1.4 6
VREF and Buffer ON, Oscillator OFF
Serial Data Clocked During the 48 Clock
1.2 Count Conversion Cycle, CCLK = SCLK
5
B
S
L
− mA 1 VDD = 5 V se − 4
nt Noi
rre 0.8 ut
nt Cu 0.6 VDD = 3 V Outp 3
Quiesce 0.4 o-Peak 2
k-t
a
e
P 1
0.2
0 0
1 10 100 1 2 4 5 8 10 16 20
Sampling Rate − ksps Gain
Figure 7 Figure 8
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SBAS124C − DECEMBER 1999 − REVISED DECEMBER 2005
INPUT BIAS CURRENT
vs
INPUT VOLTAGE
0.6
Input Impedance Inversely
0.5 Proportional to Sampling Rate
A 0.4
µ
nt − 0.3 VDD = 5 V
e
urr 0.2 VDD = 3 V
C
as 0.1
Bi
put 0
n
− I −0.1
B
II
−0.2
−0.3
−0.4
0 1 2 3 4 5 6
VI − Input Voltage − V
Figure 9
INTEGRAL LINEARITY ERROR
2
1.5
1
B 0.5
S
L
− 0
r
o
r −0.5
r
E
−1
−1.5
−2
0 1024 2048 3072 4096
Output Code
Figure 10
DIFFERENTIAL LINEARITY ERROR
2
1.5
B 1
S
L
− 0.5
r
o
r
Er 0
−0.5
−1
0 1024 2048 3072 4096
Output Code
Figure 11
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OVERVIEW
The ADS7870 is a complete data acquisition device composed of an input analog multiplexer (MUX), a
programmable gain amplifier (PGA) and an analog-to-digital (A/D) converter. Four lines of digital input/output
(I/O) are also provided. Additional circuitry provides support functions including conversion clock, voltage
reference, and serial interface for control and data retrieval.
Control and configuration of the ADS7870 are accomplished by command bytes written to internal registers
through the serial port. Command register device control includes MUX channel selection, PGA gain, A/D start
conversion command, and I/O line control. Command register configuration control includes internal voltage
reference setting and oscillator control.
Operational modes and selected functions can be activated by digital inputs at corresponding pins. Pin settable
configuration options include SCLK active-edge selection, master reset, and internal oscillator clock enable.
The ADS7870 has eight analog signal input pins, LN0 through LN7. These pins are connected to a network of
analog switches (the MUX). The inputs can be configured as 8 single-ended or 4 differential inputs, or some
combination.
The four general-purpose digital I/O pins (I/O3 through I/O0) can be made to function individually as either digital
inputs or digital outputs. These pins give the user access to four digital I/O pins through the serial interface
without having to run additional wires to the host controller.
The programmable gain amplifier (PGA) provides gains of 1, 2, 4, 5, 8, 10, 16, and 20 V/V.
The 12-bit A/D converter in the ADS7870 is a successive approximation type. The default output of the
converter is 2s complement format and can be read in a variety of ways depending on the program
configuration.
The ADS7870 internal voltage reference can be software configured for output voltages of 1.15 V, 2.048 V, or
2.5V. The reference circuit is trimmed for high initial accuracy and low temperature drift. A separate buffer
amplifier is provided to buffer the high impedance VREF output.
The voltage reference, PGA, and A/D converter use the conversion clock (CCLK) and signals derived from it.
CCLK can be either an input or output signal. The ADS7870 can divide the CCLK signal by a constant before
it is applied to the A/D converter and PGA. This allows a higher frequency system clock to be used to control
the A/D converter operation. Division factors (DF) of 1, 2, 4, and 8 are available. The signal that is actually
applied to the PGA and A/D converter is DCLK, where DCLK = CCLK/DF.
The ADS7870 is designed so that its serial interface can be conveniently used with a wide variety of
microcontrollers. It has four conventional serial interface pins: SCLK (serial data clock), DOUT (serial data out),
DIN (serial data in, which may be set bidirectional in some applications), and CS (chip select function).
The ADS7870 has ten internal user accessible registers which are used in normal operation to configure and
control the device (summarized in Figure 15).
10