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12-/14-Bit, 160/250MSPS, Ultralow-Power ADC datasheet PDF

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Preview 12-/14-Bit, 160/250MSPS, Ultralow-Power ADC datasheet

ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 12-/14-Bit, 160/250MSPS, Ultralow-Power ADC CheckforSamples:ADS4126,ADS4129,ADS4146,ADS4149 FEATURES DESCRIPTION 1 • MaximumSampleRate:250MSPS The ADS412x/4x are a family of 12-bit/14-bit 23 • UltralowPower with1.8VSingleSupply: analog-to-digital converters (ADCs) with sampling rates up to 250MSPS. These devices use innovative – 201mWTotal Powerat160MSPS design techniques to achieve high dynamic – 265mWTotal Powerat250MSPS performance, while consuming extremely low power • HighDynamicPerformance: at 1.8V supply. The devices are well-suited for multi-carrier, wide bandwidth communications – SNR:70.6dBFSat170MHz applications. – SFDR:84dBcat170MHz The ADS412x/4x have fine gain options that can be • DynamicPowerScalingwithSampleRate used to improve SFDR performance at lower • Output Interface: full-scale input ranges, especially at high input – DoubleDataRate(DDR)LVDS with frequencies. They include a dc offset correction loop ProgrammableSwingand Strength that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at – StandardSwing:350mV scaleddownpower withnolossinperformance. – LowSwing:200mV The ADS412x/4x are available in a compact QFN-48 – DefaultStrength:100ΩTermination package and are specified over the industrial – 2xStrength:50ΩTermination temperaturerange(–40°Cto+85°C) – 1.8VParallelCMOSInterfaceAlso Supported • ProgrammableGainupto6dBforSNR/SFDR Trade-Off • DCOffsetCorrection • SupportsLowInputClockAmplitudeDownTo 200mV PP • Package:QFN-48(7mm×7mm) ADS412x/ADS414xFamilyComparison SAMPLINGRATE WITHANALOGINPUTBUFFERS FAMILY 65MSPS 125MSPS 160MSPS 250MSPS 200MSPS 250MSPS ADS412x ADS4122 ADS4125 ADS4126 ADS4129 — ADS41B29 12-bitfamily ADS414x ADS4142 ADS4145 ADS4146 ADS4149 — ADS41B49 14-bitfamily 9-bit — — — — — ADS58B19 11-bit — — — — ADS58B18 — 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PowerPADisatrademarkofTexasInstrumentsIncorporated. 2 Allothertrademarksarethepropertyoftheirrespectiveowners. 3 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2009–2011,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters. ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ORDERINGINFORMATION(1) SPECIFIED PACKAGE- PACKAGE TEMPERATURE LEAD/BALL PACKAGE ORDERING TRANSPORTMEDIA, PRODUCT LEAD DESIGNATOR RANGE ECOPLAN(2) FINISH MARKING NUMBER QUANTITY GREEN(RoHS,no ADS4126IRGZR Tapeandreel,2500 ADS4126 QFN-48 RGZ –40°Cto+85°C Cu/NiPdAu AZ4126 Sb/Br) ADS4126IRGZT Tapeandreel,250 GREEN(RoHS,no ADS4129IRGZR Tapeandreel,2500 ADS4129 QFN-48 RGZ –40°Cto+85°C Cu/NiPdAu AZ4129 Sb/Br) ADS4129IRGZT Tapeandreel,250 GREEN(RoHS,no ADS4146IRGZR Tapeandreel,2500 ADS4146 QFN-48 RGZ –40°Cto+85°C Cu/NiPdAu AZ4146 Sb/Br) ADS4146IRGZT Tapeandreel,250 GREEN(RoHS,no ADS4149IRGZR Tapeandreel,2500 ADS4149 QFN-48 RGZ –40°Cto+85°C Cu/NiPdAu AZ4149 Sb/Br) ADS4149IRGZT Tapeandreel,250 (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orvisitthe deviceproductfolderatwww.ti.com. (2) EcoPlanistheplannedeco-friendlyclassification.Green(RoHS,noSb/Br):TIdefinesGreentomeanPb-Free(RoHScompatible)and freeofBromine-(Br)andAntimony-(Sb)basedflameretardants.RefertotheQualityandLead-Free(Pb-Free)Datawebsiteformore information. The ADS412x/4x family is pin-compatible with the previous generation ADS6149 family; this architecture enables easymigration.However,therearesomeimportantdifferencesbetweenthegenerations, summarizedin Table1. Table1.MIGRATINGFROMTHEADS6149FAMILY ADS6149FAMILY ADS4149FAMILY PINS Pin21isNC(notconnected) Pin21isNC(notconnected) Pin23isMODE Pin23isRESERVEDintheADS4149family.Itisreservedasadigitalcontrolpinforan(asyet)undefinedfunctioninthe next-generationADCseries. SUPPLY AVDDis3.3V AVDDis1.8V DRVDDis1.8V Nochange INPUTCOMMON-MODEVOLTAGE VCMis1.5V VCMis0.95V SERIALINTERFACE Protocol:8-bitregisteraddressand8-bitregisterdata Nochangeinprotocol Newserialregistermap EXTERNALREFERENCEMODE Supported Notsupported ADS61B49FAMILY ADS41B29/B49/ADS58B18FAMILY PINS Pin21isNC(notconnected) Pin21is3.3VAVDD_BUF(supplyfortheanaloginputbuffers) Pin23isadigitalcontrolpinfortheRESERVEDfunction. Pin23isMODE Pin23functionsasSNRBoostenable(B18only). SUPPLY AVDDis3.3V AVDDis1.8V,AVDD_BUFis3.3V DRVDDis1.8V Nochange INPUTCOMMON-MODEVOLTAGE VCMis1.5V VCMis1.7V SERIALINTERFACE Nochangeinprotocol Protocol:8-bitregisteraddressand8-bitregisterdata Newserialregistermap EXTERNALREFERENCEMODE Supported Notsupported 2 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149 ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 ABSOLUTE MAXIMUM RATINGS(1) Overoperatingfree-airtemperaturerange,unlessotherwisenoted. VALUE UNIT Supplyvoltagerange,AVDD –0.3to2.1 V Supplyvoltagerange,DRVDD –0.3to2.1 V VoltagebetweenAGNDandDRGND –0.3to0.3 V VoltagebetweenAVDDtoDRVDD(whenAVDDleadsDRVDD) 0to2.1 V VoltagebetweenDRVDDtoAVDD(whenDRVDDleadsAVDD) 0to2.1 V INP,INM –0.3tominimum(1.9,AVDD+0.3) V Voltageappliedtoinputpins CLKP,CLKM(2),DFS,OE –0.3toAVDD+0.3 V RESET,SCLK,SDATA,SEN –0.3to3.9 V Operatingfree-airtemperaturerange,T –40to+85 °C A Operatingjunctiontemperaturerange,T +125 °C J Storagetemperaturerange,T –65to+150 °C stg ESD,humanbodymodel(HBM) 2 kV (1) Stressesabovetheseratingsmaycausepermanentdamage.Exposuretoabsolutemaximumconditionsforextendedperiodsmay degradedevicereliability.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyond thosespecifiedisnotimplied. (2) WhenAVDDisturnedoff,itisrecommendedtoswitchofftheinputclock(orensurethevoltageonCLKP,CLKMislessthan|0.3V|. ThispreventstheESDprotectiondiodesattheclockinputpinsfromturningon. THERMAL INFORMATION ADS4126, ADS4129, ADS4146, THERMALMETRIC(1) ADS4149 UNITS RGZ 48PINS q Junction-to-ambientthermalresistance 29 JA q Junction-to-case(top)thermalresistance JCtop q Junction-to-boardthermalresistance 10 JB °C/W y Junction-to-topcharacterizationparameter 0.3 JT y Junction-to-boardcharacterizationparameter 9 JB q Junction-to-case(bottom)thermalresistance 1.13 JCbot (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149 ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com RECOMMENDED OPERATING CONDITIONS Overoperatingfree-airtemperaturerange,unlessotherwisenoted. ADS412x,ADS414x MIN TYP MAX UNIT SUPPLIES AVDD Analogsupplyvoltage 1.7 1.8 1.9 V DRVDD Digitalsupplyvoltage 1.7 1.8 1.9 V ANALOGINPUTS Differentialinputvoltagerange(1) 2 V PP Inputcommon-modevoltage V ±0.05 V CM Maximumanaloginputfrequencywith2V inputamplitude(2) 400 MHz PP Maximumanaloginputfrequencywith1V inputamplitude(2) 800 MHz PP CLOCKINPUT Inputclocksamplerate ADS4129/ADS4149 Low-speedmodeenabled(3) 20 80 MSPS Low-speedmodedisabled(3) >80 250 MSPS ADS4126/ADS4146 Low-speedmodeenabled(3) 20 80 MSPS Low-speedmodedisabled(3) >80 160 MSPS Inputclockamplitudedifferential(V –V ) CLKP CLKM Sinewave,ac-coupled 0.2 1.5 V PP LVPECL,ac-coupled 1.6 V PP LVDS,ac-coupled 0.7 V PP LVCMOS,single-ended,ac-coupled 1.8 V Inputclockdutycycle Low-speedmodeenabled 40 50 60 % Low-speedmodedisabled 35 50 65 % DIGITALOUTPUTS C MaximumexternalloadcapacitancefromeachoutputpintoDRGND 5 pF LOAD DifferentialloadresistancebetweentheLVDSoutputpairs(LVDS R 100 Ω LOAD mode) T Operatingfree-airtemperature –40 +85 °C A HIGHPERFORMANCEMODES(4)(5)(6) SettheMODE1registerbitstogetbestperformanceacrosssample Mode1 clockandinputsignalfrequencies. Registeraddress=03h,registerdata=03h SettheMODE2registerbittogetbestperformanceathighinput Mode2 signalfrequencies. Registeraddress=4Ah,registerdata=01h (1) With0dBgain.SeetheFineGainsectionintheApplicationInformationforrelationbetweeninputvoltagerangeandgain. (2) SeetheTheoryofOperationsectionintheApplicationInformation. (3) SeetheSerialInterfacesectionfordetailsonlow-speedmode. (4) Itisrecommendedtousethesemodestogetbestperformance.Thesemodescanbesetusingtheserialinterfaceonly. (5) SeetheSerialInterfacesectionfordetailsonregisterprogramming. (6) Notethatthesemodescannotbesetwhentheserialinterfaceisnotused(whentheRESETpinistiedhigh);seetheDevice Configurationsection. 4 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149 ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 ELECTRICAL CHARACTERISTICS: ADS4126/ADS4129 Typicalvaluesareat+25°C,AVDD=1.8V,DRVDD=1.8V,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain, andDDRLVDSinterface,unlessotherwisenoted.Minimumandmaximumvaluesareacrossthefulltemperaturerange: T =–40°CtoT =+85°C,AVDD=1.8V,andDRVDD=1.8V.Notethatafterreset,thedeviceisin0dBgainmode. MIN MAX ADS4126(160MSPS) ADS4129(250MSPS) PARAMETER TESTCONDITIONS MIN TYP MAX MIN TYP MAX UNIT Resolution 12 12 Bits fIN=10MHz 70.2 69.8 dBFS fIN=70MHz 70 69.7 dBFS SNR(signal-to-noiseratio),LVDS fIN=100MHz 69.7 69.6 dBFS fIN=170MHz 66.5 69 65.8 69 dBFS fIN=300MHz 68 68 dBFS fIN=10MHz 70.1 69.7 dBFS fIN=70MHz 70 69.4 dBFS SINAD(signal-to-noiseanddistortionratio), LVDS fIN=100MHz 69.5 69.3 dBFS fIN=170MHz 65.5 68.7 65.5 68.7 dBFS fIN=300MHz 67.3 66.8 dBFS fIN=10MHz 88 87 dBc fIN=70MHz 87 82 dBc Spurious-freedynamicrange SFDR fIN=100MHz 86.3 81 dBc fIN=170MHz 72.5 82 70 80 dBc fIN=300MHz 77.5 75 dBc fIN=10MHz 87 85 dBc fIN=70MHz 85 80 dBc Totalharmonicdistortion THD fIN=100MHz 84 79 dBc fIN=170MHz 70 81 69 79 dBc fIN=300MHz 74.5 71.5 dBc fIN=10MHz 92 90 dBc fIN=70MHz 90 85 dBc Second-harmonicdistortion HD2 fIN=100MHz 88 84 dBc fIN=170MHz 72.5 88 70 84 dBc fIN=300MHz 78 74 dBc fIN=10MHz 88 87 dBc fIN=70MHz 87 82 dBc Third-harmonicdistortion HD3 fIN=100MHz 86 81 dBc fIN=170MHz 72.5 82 70 80 dBc fIN=300MHz 77 75 dBc fIN=10MHz 92 90 dBc fIN=70MHz 91 88 dBc Worstspur (otherthansecondandthirdharmonics) fIN=100MHz 90 90 dBc fIN=170MHz 76 90 75 88 dBc fIN=300MHz 88 88 dBc f1=46MHz,f2=50MHz, –88 –88 dBFS Two-toneintermodulation eachtoneat–7dBFS IMD distortion f1=185MHz,f2=190MHz, –86 –86 dBFS eachtoneat–7dBFS Recoverytowithin1%(offinal Clock Inputoverloadrecovery value)for6dBoverloadwith 1 1 cycles sine-waveinput ACpower-supplyrejectionratio PSRR For100mVPPsignalonAVDD >30 >30 dB supply,upto10MHz Effectivenumberofbits ENOB fIN=170MHz 11.2 11.2 LSBs Differentialnonlinearity DNL fIN=170MHz –0.85 ±0.2 2.5 –0.95 ±0.2 2.5 LSBs Integratednonlinearity INL fIN=170MHz ±0.25 3.5 ±0.5 5 LSBs Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149 ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com ELECTRICAL CHARACTERISTICS: ADS4146/ADS4149 Typicalvaluesareat+25°C,AVDD=1.8V,DRVDD=1.8V,50%clockdutycycle,–1dBFSdifferentialanaloginput,1dBgain, andDDRLVDSinterface,unlessotherwisenoted.Minimumandmaximumvaluesareacrossthefulltemperaturerange: T =–40°CtoT =+85°C,AVDD=1.8V,andDRVDD=1.8V.Notethatafterreset,thedeviceisin0dBgainmode. MIN MAX ADS4146(160MSPS) ADS4149(250MSPS) PARAMETER TESTCONDITIONS MIN TYP MAX MIN TYP MAX UNIT Resolution 14 14 Bits fIN=10MHz 72.2 71.9 dBFS fIN=70MHz 72 71.4 dBFS SNR(signal-to-noiseratio),LVDS fIN=100MHz 71.5 71.4 dBFS fIN=170MHz 68.5 70.8 67.5 70.6 dBFS fIN=300MHz 69 69 dBFS fIN=10MHz 72 71.6 dBFS fIN=70MHz 71.8 71 dBFS SINAD(signal-to-noiseanddistortionratio), LVDS fIN=100MHz 71.4 70.9 dBFS fIN=170MHz 67.5 70.4 66 69.4 dBFS fIN=300MHz 68.2 67.4 dBFS fIN=10MHz 88 87 dBc fIN=70MHz 87 82 dBc Spurious-freedynamicrange SFDR fIN=100MHz 86 81 dBc fIN=170MHz 74.5 82 72 84 dBc fIN=300MHz 77 75 dBc fIN=10MHz 86.5 85 dBc fIN=70MHz 85 80 dBc Totalharmonicdistortion THD fIN=100MHz 84 79 dBc fIN=170MHz 72 81 71 80.5 dBc fIN=300MHz 74.5 71.5 dBc fIN=10MHz 91 89 dBc fIN=70MHz 90 85 dBc Second-harmonicdistortion HD2 fIN=100MHz 88 84 dBc fIN=170MHz 74.5 88 72 84 dBc fIN=300MHz 79 75 dBc fIN=10MHz 88 87 dBc fIN=70MHz 87 82 dBc Third-harmonicdistortion HD3 fIN=100MHz 86 81 dBc fIN=170MHz 74.5 82 72 82 dBc fIN=300MHz 77 75 dBc fIN=10MHz 91 90 dBc fIN=70MHz 90 88 dBc Worstspur (otherthansecondandthirdharmonics) fIN=100MHz 90 90 dBc fIN=170MHz 78 90 77 88 dBc fIN=300MHz 88 88 dBc f1=46MHz,f2=50MHz, –88 –88 dBFS Two-toneintermodulation eachtoneat–7dBFS IMD distortion f1=185MHz,f2=190MHz, –86 –86 dBFS eachtoneat–7dBFS Recoverytowithin1%(offinal Clock Inputoverloadrecovery value)for6dBoverloadwith 1 1 cycles sine-waveinput ACpower-supplyrejectionratio PSRR For100mVPPsignalonAVDD >30 >30 dB supply,upto10MHz Effectivenumberofbits ENOB fIN=170MHz 11.5 11.3 LSBs Differentialnonlinearity DNL fIN=170MHz –0.95 ±0.5 –0.95 ±0.5 LSBs Integratednonlinearity INL fIN=170MHz ±2 ±4.5 ±2 ±5 LSBs 6 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149 ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 ELECTRICAL CHARACTERISTICS: GENERAL Typicalvaluesareat+25°C,AVDD=1.8V,DRVDD=1.8V,50%clockdutycycle,and0dBgain,unlessotherwisenoted. Minimumandmaximumvaluesareacrossthefulltemperaturerange:T =–40°CtoT =+85°C,AVDD=1.8V,and MIN MAX DRVDD=1.8V. ADS4126/ADS4146(160MSPS) ADS4129/ADS4149(250MSPS) PARAMETER MIN TYP MAX MIN TYP MAX UNIT ANALOGINPUTS Differentialinputvoltagerange 2 2 VPP Differentialinputresistance(atdc);seeFigure114 >1 >1 MΩ Differentialinputcapacitance;seeFigure115 4 4 pF Analoginputbandwidth 550 550 MHz Analoginputcommon-modecurrent(perinputpin) 0.6 0.6 µA/MSPS Common-modeoutputvoltage VCM 0.95 0.95 V VCMoutputcurrentcapability 4 4 mA DCACCURACY Offseterror –15 2.5 15 –15 2.5 15 mV Temperaturecoefficientofoffseterror 0.003 0.003 mV/°C Gainerrorasaresultofinternalreference inaccuracyalone EGREF –2 2 –2 2 %FS Gainerrorofchannelalone EGCHAN –0.2 –0.2 –1 %FS TemperaturecoefficientofEGCHAN 0.001 0.001 Δ%/°C POWERSUPPLY IAVDD 72 83 99 113 mA Analogsupplycurrent IDRVDD(1) Outputbuffersupplycurrent 39.5 51 47 mA LVDSinterfacewith100Ωexternaltermination LowLVDSswing(200mV) IDRVDD Outputbuffersupplycurrent 51 63 59 72 mA LVDSinterfacewith100Ωexternaltermination StandardLVDSswing(350mV) IDRVDDoutputbuffersupplycurrent(1)(2) CMOSinterface(2) 26 35 mA 8pFexternalloadcapacitance fIN=2.5MHz Analogpower 130 179 mW LVDSinterface,lowLVDSswing 71.1 84.6 mW Digitalpower CMOSinterface(2) 47 63 mW 8pFexternalloadcapacitance fIN=2.5MHz Globalpower-down 10 25 10 25 mW Standby 185 185 mW (1) ThemaximumDRVDDcurrentwithCMOSinterfacedependsontheactualloadcapacitanceonthedigitaloutputlines.Notethatthe maximumrecommendedloadcapacitanceoneachdigitaloutputlineis10pF. (2) InCMOSmode,theDRVDDcurrentscaleswiththesamplingfrequency,theloadcapacitanceonoutputpins,inputfrequency,andthe supplyvoltage(seetheCMOSInterfacePowerDissipationsectionintheApplicationInformation). Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149 ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com DIGITAL CHARACTERISTICS Typicalvaluesareat+25°C,AVDD=1.8V,DRVDD=1.8V,and50%clockdutycycle,unlessotherwisenoted.Minimumand maximumvaluesareacrossthefulltemperaturerange:T =–40°CtoT =+85°C,AVDD=1.8V,andDRVDD=1.8V. MIN MAX ADS4126,ADS4129,ADS4146,ADS4149 PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DIGITALINPUTS(RESET,SCLK,SDATA,SEN,OE) High-levelinputvoltage RESET,SCLK,SDATA,and 1.3 V SENsupport1.8Vand3.3V Low-levelinputvoltage CMOSlogiclevels 0.4 V High-levelinputvoltage OEonlysupports1.8VCMOS 1.3 V Low-levelinputvoltage logiclevels 0.4 V High-levelinputcurrent:SDATA,SCLK(1) VHIGH=1.8V 10 µA High-levelinputcurrent:SEN VHIGH=1.8V 0 µA Low-levelinputcurrent:SDATA,SCLK VLOW=0V 0 µA Low-levelinputcurrent:SEN VLOW=0V 10 µA DIGITALOUTPUTS(CMOSINTERFACE:D0TOD13,OVR_SDOUT) High-leveloutputvoltage DRVDD–0.1 DRVDD V Low-leveloutputvoltage 0 0.1 V DIGITALOUTPUTS(LVDSINTERFACE:DA0P/MTODA13P/M,DB0P/MTODB13P/M,CLKOUTP/M) High-leveloutputvoltage(2) VODH StandardswingLVDS 270 +350 430 mV Low-leveloutputvoltage(2) VODL StandardswingLVDS –430 –350 –270 mV High-leveloutputvoltage(2) VODH LowswingLVDS +200 mV Low-leveloutputvoltage(2) VODL LowswingLVDS –200 mV Outputcommon-modevoltage VOCM 0.85 1.05 1.25 V (1) SDATAandSCLKhaveaninternal180kΩpull-downresistor. (2) Withanexternal100Ωtermination. 8 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149 ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 PIN CONFIGURATION (LVDS MODE) RGZPACKAGE(1) QFN-48 (TOPVIEW) P M 1_ 1_ P M P M P M P M P M 1 1 _ _ _ _ _ _ _ _ _ _ D D 9 9 7 7 5 5 3 3 1 1 _ _ D D D D D D D D D D 0 0 _ _ _ _ _ _ _ _ _ _ 1 1 8 8 6 6 4 4 2 2 0 0 D D D D D D D D D D D D 48 47 46 45 44 43 42 41 40 39 38 37 DRGND 1 36 DRGND DRVDD 2 35 DRVDD OVR_SDOUT 3 34 NC CLKOUTM 4 33 NC CLKOUTP 5 32 NC DFS 6 31 NC OE 7 30 RESET AVDD 8 29 SCLK AGND 9 28 SDATA CLKP 10 27 SEN CLKM 11 26 AVDD AGND 12 25 AGND 13 14 15 16 17 18 19 20 21 22 23 24 M D P M D D D D C D D D C N N N N D N D N D E D V G I I G V G V V V V A A A A A A R A E S E R (1) ThePowerPADisconnectedtoDRGND. Figure 1. ADS412xLVDSPinout Copyright©2009–2011,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149 ADS4126, ADS4129 ADS4146, ADS4149 SBAS483G–NOVEMBER2009–REVISEDJANUARY2011 www.ti.com RGZPACKAGE(2) QFN-48 (TOPVIEW) P M P M 3_ 3_ 1_ 1_ P M P M P M P M 1 1 1 1 _ _ _ _ _ _ _ _ D D D D 9 9 7 7 5 5 3 3 _ _ _ _ D D D D D D D D 2 2 0 0 _ _ _ _ _ _ _ _ 1 1 1 1 8 8 6 6 4 4 2 2 D D D D D D D D D D D D 48 47 46 45 44 43 42 41 40 39 38 37 DRGND 1 36 DRGND DRVDD 2 35 DRVDD OVR_SDOUT 3 34 D0_D1_P CLKOUTM 4 33 D0_D1_M CLKOUTP 5 32 NC DFS 6 31 NC OE 7 30 RESET AVDD 8 29 SCLK AGND 9 28 SDATA CLKP 10 27 SEN CLKM 11 26 AVDD AGND 12 25 AGND 13 14 15 16 17 18 19 20 21 22 23 24 M D P M D D D D C D D D C N N N N D N D N D E D V G I I G V G V V V V A A A A A A R A E S E R (2) ThePowerPAD™isconnectedtoDRGND. Figure 2. ADS414xLVDSPinout ADS412x,ADS414xPinAssignments(LVDSMode) #OF PINNAME PINNUMBER PINS FUNCTION DESCRIPTION AVDD 8,18,20,22,24,26 6 I 1.8Vanalogpowersupply AGND 9,12,14,17,19,25 6 I Analogground CLKP 10 1 I Differentialclockinput,positive CLKM 11 1 I Differentialclockinput,negative INP 15 1 I Differentialanaloginput,positive INM 16 1 I Differentialanaloginput,negative Outputsthecommon-modevoltage(0.95V)thatcanbeusedexternallytobiasthe VCM 13 1 O analoginputpins. SerialinterfaceRESETinput. Whenusingtheserialinterfacemode,theinternalregistersmustinitializethrough hardwareRESETbyapplyingahighpulseonthispinorbyusingthesoftwarereset RESET 30 1 I option;refertotheSerialInterfacesection. WhenRESETistiedhigh,theinternalregistersareresettothedefaultvalues.Inthis condition,SENcanbeusedasananalogcontrolpin. RESEThasaninternal180kΩpull-downresistor. ThispinfunctionsasaserialinterfaceclockinputwhenRESETislow.WhenRESETis SCLK 29 1 I high,SCLKhasnofunctionandshouldbetiedtoground.Thispinhasaninternal 180kΩpull-downresistor. ThispinfunctionsasaserialinterfacedatainputwhenRESETislow.WhenRESETis SDATA 28 1 I high,SDATAfunctionsasaSTANDBYcontrolpin(seeTable9).Thispinhasan internal180kΩpull-downresistor. ThispinfunctionsasaserialinterfaceenableinputwhenRESETislow.WhenRESET SEN 27 1 I ishigh,SENhasnofunctionandshouldbetiedtoAVDD.Thispinhasaninternal 180kΩpull-upresistortoAVDD. 10 SubmitDocumentationFeedback Copyright©2009–2011,TexasInstrumentsIncorporated ProductFolderLink(s):ADS4126ADS4129 ADS4146 ADS4149

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analog-to-digital converters (ADCs) with sampling . (2) When AVDD is turned off, it is recommended to switch off the input clock (or ensure the
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