12-, 14-, and 16-Bit, 8-Channel, Simultaneous Sampling ADCs PDF
Preview 12-, 14-, and 16-Bit, 8-Channel, Simultaneous Sampling ADCs
Product Order Technical Tools & Support & Reference Folder Now Documents Software Community Design ADS8528,ADS8548,ADS8568 SBAS543C–AUGUST2011–REVISEDFEBRUARY2016 ADS85x8 12-, 14-, and 16-Bit, 8-Channel, Simultaneous Sampling ADCs 1 Features 3 Description • Familyof12-,14-,and16-Bit,Pin-andSoftware- The ADS85x8 contain eight low-power, 12-, 14-, or 1 16-bit, successive approximation register (SAR)- CompatibleADCs based analog-to-digital converters (ADCs) with true • MaximumDataRateperChannel: bipolar inputs. These channels are grouped in four – ADS8528:650kSPS(PAR)or pairs, thus allowing simultaneous high-speed signal 480kSPS(SER) acquisitionofupto650kSPS. – ADS8548:600kSPS(PAR)or The devices support selectable parallel or serial 450kSPS(SER) interface with daisy-chain capability. The – ADS8568:510kSPS(PAR)or programmable reference allows handling of analog input signalswithamplitudesupto±12V. 400kSPS(SER) • ExcellentACPerformance: TheADS85x8familysupportsanauto-sleepmodefor minimum power dissipation and is available in both – Signal-to-NoiseRatio: 64-pin VQFN and LQFP packages. The entire family ADS8528:73.9dB,ADS8548:85dB, is specified over a temperature range of –40°C to ADS8568:91.5dB +125°C. – TotalHarmonicDistortion: ADS8528:–89dB,ADS8548: –91dB, DeviceInformation(1) ADS8568:–94dB PARTNUMBER PACKAGE BODYSIZE(NOM) • Programmable,BufferedInternalReference: VQFN(64) 9.00mm×9.00mm ADS85x8 0.5V–2.5Vor0.5V–3.0VSupportsInput LQFP(64) 10.00mm×10.00mm VoltageRangesupto±12V (1) For all available packages, see the orderable addendum at • SelectableParallelorSerial Interface theendofthedatasheet. • ScalableLow-PowerOperationUsingAuto-Sleep Mode:Only32mWat10kSPS SimplifiedBlockDiagram • FullySpecifiedOverExtendedIndustrial TemperatureRange Clock Generator 2 Applications • ProtectionRelays CH_A0 SAR ADC Control • PowerQualityMeasurement Control CH_A1 SAR ADC Logic Signal • Multi-AxisMotorControls Bus • ProgrammableLogicControllers CH_B0 SAR ADC • IndustrialDataAcquisition CH_B1 SAR ADC SNRvsTemperature Config Register 94 CH_C0 SAR ADC 92 B) 90 CH_C1 SAR ADC d 88 Ratio ( 8846 CH_D0 SAR ADC I/O Pora Sraellreiall se 82 Data Bus Noi 80 ADS8568 CH_D1 SAR ADC o- ADS8548 al-t 78 ADS8528 gn 76 Si 74 REFIO String DAC 2.5-V, 3-V Reference 72 70 −40 −25 −10 5 20 35 50 65 80 95 110 125 Temperature (°C) G016 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA. ADS8528,ADS8548,ADS8568 SBAS543C–AUGUST2011–REVISEDFEBRUARY2016 www.ti.com Table of Contents 1 Features.................................................................. 1 9 DetailedDescription............................................ 26 2 Applications........................................................... 1 9.1 Overview.................................................................26 3 Description............................................................. 1 9.2 FunctionalBlockDiagram.......................................27 4 RevisionHistory..................................................... 2 9.3 FeatureDescription.................................................28 9.4 DeviceFunctionalModes........................................34 5 DeviceComparisonTable..................................... 4 9.5 RegisterMaps ........................................................39 6 PinConfigurationandFunctions......................... 4 10 ApplicationandImplementation........................ 41 7 Specifications......................................................... 9 10.1 ApplicationInformation..........................................41 7.1 AbsoluteMaximumRatings......................................9 10.2 TypicalApplication................................................41 7.2 ESDRatings..............................................................9 11 PowerSupplyRecommendations..................... 46 7.3 RecommendedOperatingConditions.......................9 12 Layout................................................................... 46 7.4 ThermalInformation..................................................9 7.5 ElectricalCharacteristics:General..........................10 12.1 LayoutGuidelines.................................................46 7.6 ElectricalCharacteristics:ADS8528.......................13 12.2 LayoutExample....................................................47 7.7 ElectricalCharacteristics:ADS8548.......................14 13 DeviceandDocumentationSupport................. 48 7.8 ElectricalCharacteristics:ADS8568.......................15 13.1 DocumentationSupport .......................................48 7.9 SerialInterfaceTimingRequirements.....................16 13.2 RelatedLinks........................................................48 7.10 ParallelInterfaceTimingRequirements(Read 13.3 CommunityResources..........................................48 Access)....................................................................17 13.4 Trademarks...........................................................48 7.11 ParallelInterfaceTimingRequirements(Write 13.5 ElectrostaticDischargeCaution............................48 Access)....................................................................17 13.6 Glossary................................................................48 7.12 TypicalCharacteristics..........................................20 14 Mechanical,Packaging,andOrderable 8 ParameterMeasurementinformation................26 Information........................................................... 48 8.1 EquivalentCircuits..................................................26 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionB(November2015)toRevisionC Page • ChangedFigure45:changedcapacitorvaluesfrom820nFto820pF .............................................................................. 42 ChangesfromRevisionA(October2011)toRevisionB Page • AddedESDRatingstable,RecommendedOperatingConditionstable,FeatureDescriptionsection,Device FunctionalModessection,RegisterMapssection,ApplicationandImplementationsection,PowerSupply Recommendationssection,Layoutsection,DeviceandDocumentationSupportsection,andMechanical, Packaging,andOrderableInformationsection...................................................................................................................... 1 • ChangedtitleofDeviceComparisonTable,deletedfootnote1 ............................................................................................ 4 • AddedStoragetemperatureparametertoAbsoluteMaximumRatingstable........................................................................ 9 • ChangedClockcyclesperconversiontobeasingleparameterinsteadofpartoft parameterinSerialInterface CONV TimingRequirementstable.................................................................................................................................................. 16 • Changedt parameterinSerialInterfaceTimingRequirementstable............................................................................ 16 BUFS • Addedfootnote3toSerialInterfaceTimingRequirementstable......................................................................................... 16 • ChangedClockcyclesperconversiontobeasingleparameterinsteadofpartoft parameterinParallel CONV InterfaceTimingRequirements(ReadAccess)table .......................................................................................................... 17 • Changedt parameterinParallelInterfaceTimingRequirements(ReadAccess)table ............................................... 17 BUCS • Addedfootnote3toParallelInterfaceTimingRequirements(ReadAccess)table ............................................................ 17 • ChangedDataReadoutandBUSY/INTSignalsection........................................................................................................ 30 • AddedSequentialOperationsection.................................................................................................................................... 31 • ChangeddescriptionofinitiatinganewconversioninResetandPower-DownModessection.......................................... 38 2 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8528 ADS8548 ADS8568 ADS8528,ADS8548,ADS8568 www.ti.com SBAS543C–AUGUST2011–REVISEDFEBRUARY2016 ChangesfromOriginal(August2011)toRevisionA Page • DeletedINLcolumnfromFamily/OrderingInformationtable................................................................................................. 4 • ChangedDCAccuracy,INLparameterinADS8568ElecticalChatacteristicstable............................................................ 15 Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:ADS8528 ADS8548 ADS8568 ADS8528,ADS8548,ADS8568 SBAS543C–AUGUST2011–REVISEDFEBRUARY2016 www.ti.com 5 Device Comparison Table RESOLUTION MAXIMUMDATARATE:PAR,SER SNR THD PRODUCT (Bits) (kSPSperChannel) (dB,Typ) (dB,Typ) ADS8528 12 650,480 73.9 –89 ADS8548 14 600,450 85 –91 ADS8568 16 510,400 91.5 –94 6 Pin Configuration and Functions RGCPackage 64-PinVQFN TopView _C0 FCP ND DD FCN _C1 ND DD FIO FN _B1 FBN DD ND FBP _B0 H E G V E H G V E E H E V G E H C R A A R C A A R R C R A A R C 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 HVSS 1 48 HVDD CH_D1 2 47 CH_A1 REFDN 3 46 REFAN AVDD 4 45 AVDD AGND 5 44 AGND REFDP 6 43 REFAP CH_D0 7 42 CH_A0 PAR/SER 8 7.3-mm x 7.3-mm 41 HW/SW STBY 9 Exposed Thermal Pad 40 CONVST_D RESET 10 39 CONVST_C REFEN/WR 11 38 CONVST_B RD 12 37 CONVST_A CS/FS 13 36 ASLEEP AVDD 14 35 BUSY/INT AGND 15 34 RANGE/XCLK DB15/SDO_D 16 33 DB0/DCIN_D 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 DB14/SDO_C DB13/SDO_B DB12/SDO_A 1/REFBUFEN DB10/SCLK DB9/SDI DB8/DCEN DGND DVDD DB7 DB6/SEL_B DB5/SEL_CD DB4 DB3/DCIN_A DB2/DCIN_B DB1/DCIN_C 1 B D 4 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8528 ADS8548 ADS8568 ADS8528,ADS8548,ADS8568 www.ti.com SBAS543C–AUGUST2011–REVISEDFEBRUARY2016 PMPackage 64-PinLQFP TopView _C0 FCP ND DD FCN _C1 ND DD FIO FN _B1 FBN DD ND FBP _B0 H E G V E H G V E E H E V G E H C R A A R C A A R R C R A A R C 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 HVSS 1 48 HVDD CH_D1 2 47 CH_A1 REFDN 3 46 REFAN AVDD 4 45 AVDD AGND 5 44 AGND REFDP 6 43 REFAP CH_D0 7 42 CH_A0 PAR/SER 8 41 HW/SW STBY 9 40 CONVST_D RESET 10 39 CONVST_C REFEN/WR 11 38 CONVST_B RD 12 37 CONVST_A CS/FS 13 36 ASLEEP AVDD 14 35 BUSY/INT AGND 15 34 RANGE/XCLK DB15/SDO_D 16 33 DB0/DCIN_D 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 DB14/SDO_C DB13/SDO_B DB12/SDO_A 1/REFBUFEN DB10/SCLK DB9/SDI DB8/DCEN DGND DVDD DB7 DB6/SEL_B DB5/SEL_CD DB4 DB3/DCIN_A DB2/DCIN_B DB1/DCIN_C 1 B D Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:ADS8528 ADS8548 ADS8568 ADS8528,ADS8548,ADS8568 SBAS543C–AUGUST2011–REVISEDFEBRUARY2016 www.ti.com PinFunctions PIN DESCRIPTION TYPE(1) NAME NO. PARALLELINTERFACE(PAR/SER=0) SERIALINTERFACE(PAR/SER=1) 5,15,44, AGND P Analogground;connecttotheanaloggroundplane. 51,58,62 Auto-sleepenableinput. Whenlow,thedeviceoperatesinnormalmode. Whenhigh,thedevicefunctionsinauto-sleepmodewheretheholdmodeandtheactualconversionisactivated ASLEEP 36 DI sixconversionclock(tCCLK)cyclesafterissuingaconversionstartusingaCONVST_x.Thismodeis recommendedtosavepowerifthedevicerunsatalowerdatarate;seetheResetandPower-DownModes sectionformoredetails. 4,14,45, Analogpowersupply. AVDD P 52,57,61 DecoupleaccordingtothePowerSupplyRecommendationssection. WhenCONFIGbitC27=0(BUSY/INT),thispinisaconverterbusystatusoutput. Thispintransitionshighwhenaconversionisstartedandtransitionslowforasingleconversionclockcycle (tCCLK)wheneverachannelpairconversioniscompletedandstayslowwhentheconversionofthelastchannel paircompletes. BUSY/INT 35 DO WhenbitC27=1(BUSY/INTinCONFIG),thispinisaninterruptoutput.Thispintransitionshighaftera conversioncompletesandremainshighuntilthenextreadaccess.Thismodecanonlybeusedifalleight channelsaresampledsimultaneously(allCONVST_xtiedtogether).ThepolarityoftheBUSY/INToutputcanbe changedusingtheC26bit(BUSYL/H)intheConfigurationregister. AnaloginputofchannelA0;channelAisthemasterchannelpairthatisalwaysactive. TheinputvoltagerangeiscontrolledbytheRANGEpininhardwaremodeorbyConfigurationregister(CONFIG) CH_A0 42 AI bitC24(RANGE_A)insoftwaremode.Incaseswherechannelpairsofthedeviceareusedatdifferentdata rates,channelpairAmustalwaysrunatthehighestdatarate. AnaloginputofchannelA1;channelAisthemasterchannelpairthatisalwaysactive. TheinputvoltagerangeiscontrolledbytheRANGEpininhardwaremodeorbyCONFIGbitC24(RANGE_A)in CH_A1 47 AI softwaremode.Incaseswherechannelpairsofthedeviceareusedatdifferentdatarates,channelpairAmust alwaysrunatthehighestdatarate. AnaloginputofchannelB0.TheinputvoltagerangeiscontrolledbytheRANGEpininhardwaremodeorby CH_B0 49 AI CONFIGbitC23(RANGE_B)insoftwaremode. AnaloginputofchannelB1.TheinputvoltagerangeiscontrolledbytheRANGEpininhardwaremodeorby CH_B1 54 AI CONFIGbitC23(RANGE_B)insoftwaremode. AnaloginputofchannelC0.TheinputvoltagerangeiscontrolledbytheRANGEpininhardwaremodeorby CH_C0 64 AI CONFIGbitC21(RANGE_C)insoftwaremode. AnaloginputofchannelC1.TheinputvoltagerangeiscontrolledbytheRANGEpininhardwaremodeorby CH_C1 59 AI CONFIGbitC21(RANGE_C)insoftwaremode. AnaloginputofchannelD0.TheinputvoltagerangeiscontrolledbytheRANGEpininhardwaremodeorby CH_D0 7 AI CONFIGbitC19(RANGE_D)insoftwaremode.ThispincanbepowereddownusingCONFIGbitC18(PD_D)in softwaremode. AnaloginputofchannelD1.TheinputvoltagerangeiscontrolledbytheRANGEpininhardwaremodeorby CH_D1 2 AI CONFIGbitC19(RANGE_D)insoftwaremode.ThispincanbepowereddownusingCONFIGbitC18(PD_D)in softwaremode. ConversionstartofchannelpairA. TherisingedgeofthissignalinitiatessimultaneousconversionofanalogsignalsatinputsCH_A[1:0]. CONVST_A 37 DI Thissignalresetstheinternalchannelstatemachinethatcausesthedataoutputtostartwithconversionresults ofchannelA0withthenextreadaccess. ConversionstartofchannelpairB. CONVST_B 38 DI TherisingedgeofthissignalinitiatessimultaneousconversionofanalogsignalsatinputsCH_B[1:0]. ConversionstartofchannelpairC. CONVST_C 39 DI TherisingedgeofthissignalinitiatessimultaneousconversionofanalogsignalsatinputsCH_C[1:0]. ConversionstartofchannelpairD. CONVST_D 40 DI TherisingedgeofthissignalinitiatessimultaneousconversionofanalogsignalsatinputsCH_D[1:0]. Chip-selectinput. Framesynchronization. CS/FS 13 DI,DI Whenlow,theparallelinterfaceisenabled. TheFSfallingedgecontrolstheframetransfer. Whenhigh,theinterfaceisdisabled. WhenDCEN=1andSEL_CD=1,thispinisthedaisy-chaindata DB0/DCIN_D 33 DIO,DI Databit0(LSB)input/output inputforSDO_Dofthepreviousdeviceinthechain. WhenDCEN=0,connecttoDGND. WhenDCEN=1andSEL_CD=1,thispinisthedaisy-chaindata DB1/DCIN_C 32 DIO,DI Databit1input/output inputforSDO_Cofthepreviousdeviceinthechain. WhenDCEN=0,connecttoDGND. WhenDCEN=1andSEL_B=1,thispinisthedaisy-chaindata DB2/DCIN_B 31 DIO,DI Databit2input/output inputforSDO_Bofthepreviousdeviceinthechain. WhenDCEN=0,connecttoDGND. WhenDCEN=1,thispinisthedaisy-chaindatainputforSDO_A DB3/DCIN_A 30 DIO,DI Databit3input/output ofthepreviousdeviceinthechain.WhenDCEN=0,connectto DGND. (1) AI=analoginput;AIO=analoginput/output;DI=digitalinput;DIO=digitalinput/output;DO=digitaloutput;andP=powersupply. 6 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8528 ADS8548 ADS8568 ADS8528,ADS8548,ADS8568 www.ti.com SBAS543C–AUGUST2011–REVISEDFEBRUARY2016 PinFunctions (continued) PIN DESCRIPTION TYPE(1) NAME NO. PARALLELINTERFACE(PAR/SER=0) SERIALINTERFACE(PAR/SER=1) DB4 29 DIO Databit4input/output ConnecttoDGND SelectSDO_CandSDO_Dinput. Whenhigh,datafromchannelpairCareavailableonSDO_Cand datafromchannelpairDareavailableonSDO_D.Whenlowand DB5/SEL_CD 28 DIO,DI Databit5input/output SEL_B=1,datafromchannelpairsAandCareavailableon SDO_AanddatafromchannelpairsBandDareavailableon SDO_B.WhenlowandSEL_B=0,datafromalleightchannels areavailableonSDO_A. SelectSDO_Binput. Whenlow,SDO_Bisdisabledanddatafromalleightchannelsare onlyavailablethroughSDO_A. DB6/SEL_B 27 DIO,DI Databit6input/output WhenhighandSEL_CD=0,datafromchannelpairsBandDare availableonSDO_B.WhenSEL_CD=1,datafromchannelpairB areavailableonSDO_B. DB7 26 DIO Databit7input/output MustbeconnectedtoDGND Daisy-chainenableinput. DB8/DCEN 23 DIO,DI Databit8input/output Whenhigh,DB[3:0]serveasdaisy-chaininputsDCIN_[A:D]. Ifdaisy-chainmodeisnotused,connecttoDGND. Hardwaremode(HW/SW=0):connecttoDGND. DB9/SDI 22 DIO,DI Databit9input/output Softwaremode(HW/SW=1):serialdatainput. DB10/SCLK 21 DIO,DI Databit10input/output Serialinterfaceclockinput. Hardwaremode(HW/SW=0):referencebufferenableinput. Whenlow,allinternalreferencebuffersareenabled(mandatoryif internalreferenceisused). DB11/ 20 DIO,DI Databit11input/output. Whenhigh,allreferencebuffersaredisabled. REFBUFEN OutputisMSBfortheADS8528. Softwaremode(HW/SW=1):connecttoDGNDorDVDD. TheinternalreferencebuffersarecontrolledbyCONFIGbitC14 (REFBUFEN). DataoutputforchannelpairA. WhenSEL_CD=0,datafromchannelpairCarealsoavailableon Databit12input/output. DB12/SDO_A 19 DIO,DO thisoutput. OutputissignextensionfortheADS8528. WhenSEL_CD=0andSEL_B=0,SDO_Afunctionsassingle dataoutputforalleightchannels. Databit13input/output. WhenSEL_B=1,thispinisthedataoutputforchannelpairB. DB13/SDO_B 18 DIO,DO OutputissignextensionfortheADS8528 WhenSEL_B=0,tiethispintoDGND.WhenSEL_CD=0,data andMSBfortheADS8548. fromchannelpairDarealsoavailableonthisoutput. Databit14input/output. WhenSEL_CD=1,thispinisthedataoutputforchannelpairC. DB14/SDO_C 17 DIO,DO OutputissignextensionfortheADS8528 WhenSEL_CD=0,tiethispintoDGND. andADS8548. Databit15(MSB)input/output. WhenSEL_CD=1,thispinisthedataoutputforchannelpairD. DB15/SDO_D 16 DIO,DO OutputissignextensionfortheADS8528 WhenSEL_CD=0,tiethispintoDGND. andADS8548. DGND 24 P BufferI/Oground,connecttodigitalgroundplane BufferI/Osupply,connecttodigitalsupply. DVDD 25 P DecoupleaccordingtothePowerSupplyRecommendationssection. Positivesupplyvoltagefortheanaloginputs. HVDD 48 P DecoupleaccordingtothePowerSupplyRecommendationssection. Negativesupplyvoltagefortheanaloginputs. HVSS 1 P DecoupleaccordingtothePowerSupplyRecommendationssection. Modeselectioninput. Whenlow,hardwaremodeisselectedandthedevicefunctionsaccordingtothesettingsoftheexternalpins. HW/SW 41 DI Whenhigh,softwaremodeisselectedandthedeviceisconfiguredbywritingtotheConfigurationregister (CONFIG). Interfacemodeselectioninput. PAR/SER 8 DI Whenlow,theparallelinterfaceisselected.Whenhigh,theserialinterfaceisenabled. Hardwaremode(HW/SW=0):analoginputvoltagerangeselectinput. Whenlow,theanaloginputvoltagerangeis±4VREF.Whenhigh,theanaloginputvoltagerangeis±2VREF. RANGE/XCLK 34 DI/DI/DO Softwaremode(HW/SW=1):thispinisanexternalconversionclockinputifCONFIGbitC29=1(CLKSEL);or aninternalconversionclockoutputifCONFIGbitC28=1(CLKOUT_EN). Ifthispinisnotused,connecttoDGND. Readdatainput. Whenlow,theparalleldataoutputis RD 12 DI/DI MustbeconnectedtoDGND. enabled(ifCS=0).Whenhigh,thedata outputisdisabled. Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:ADS8528 ADS8548 ADS8568 ADS8528,ADS8548,ADS8568 SBAS543C–AUGUST2011–REVISEDFEBRUARY2016 www.ti.com PinFunctions (continued) PIN DESCRIPTION TYPE(1) NAME NO. PARALLELINTERFACE(PAR/SER=0) SERIALINTERFACE(PAR/SER=1) DecouplingcapacitorinputforreferenceofchannelpairA. REFAN 46 AI ConnecttothedecouplingcapacitorandAGNDaccordingtothePowerSupplyRecommendationssection. DecouplingcapacitorinputforreferenceofchannelpairA. REFAP 43 AI ConnecttothedecouplingcapacitoraccordingtothePowerSupplyRecommendationssection. DecouplingcapacitorinputforreferenceofchannelpairB. REFBN 53 AI ConnecttothedecouplingcapacitorandAGNDaccordingtothePowerSupplyRecommendationssection. DecouplingcapacitorinputforreferenceofchannelpairB. REFBP 50 AI ConnecttothedecouplingcapacitoraccordingtothePowerSupplyRecommendationssection. DecouplingcapacitorinputforreferenceofchannelpairC. REFCN 60 AI ConnecttothedecouplingcapacitorandAGNDaccordingtothePowerSupplyRecommendationssection. DecouplingcapacitorinputforreferenceofchannelpairC. REFCP 63 AI ConnecttothedecouplingcapacitoraccordingtothePowerSupplyRecommendationssection. DecouplingcapacitorinputforreferenceofchannelpairD. REFDN 3 AI ConnecttothedecouplingcapacitorandAGNDaccordingtothePowerSupplyRecommendationssection. DecouplingcapacitorinputforthechannelpairDreference. REFDP 6 AI ConnecttothedecouplingcapacitoraccordingtothePowerSupplyRecommendationssection. Hardwaremode(HW/SW=0):internal referenceenableinput. Hardwaremode(HW/SW=0):internalreferenceenableinput. Whenhigh,theinternalreferenceisenabled Whenhigh,theinternalreferenceisenabled(thereferencebuffers (thereferencebuffersarealsoenabled). arealsoenabled). Whenlow,theinternalreferenceisdisabled Whenlow,theinternalreferenceisdisabledandanexternal REFEN/WR 11 DI/DI andanexternalreferenceisappliedat referenceisappliedatREFIO. REFIO. Softwaremode(HW/SW=1):writeinput. TheparalleldatainputisenabledwhenCS Softwaremode(HW/SW=1):connecttoDGNDorDVDD.The andWRarelow.Theinternalreferenceis internalreferenceisenabledbyCONFIGbitC15(REFEN). enabledbyCONFIGbitC15(REFEN). Referencevoltageinput/output. TheinternalreferenceisenabledbytheREFEN/WRpininhardwaremodeorbyCONFIGbitC15(REFEN)in REFIO 56 AIO softwaremode.Theoutputvalueiscontrolledbytheinternaldigital-to-analogconverter(DAC),CONFIGbits C[9:0].ConnecttoadecouplingcapacitoraccordingtothePowerSupplyRecommendationssection. Negativereferenceinput/outputpin. REFN 55 AI ConnecttoadecouplingcapacitorandAGNDaccordingtothePowerSupplyRecommendationssection. Resetinput,activehigh. RESET 10 DI ThispinabortsanyongoingconversionsandresetstheinternalConfigurationregister(CONFIG)to000003FFh. Avalidresetpulsemustbeatleast50nslong. Hardwaremode(HW/SW=0):standbymodeinput. Whenlow,theentiredeviceispowereddown(includingtheinternalconversionclocksourceandreference). STBY 9 DI Whenhigh,thedeviceoperatesinnormalmode. Softwaremode(HW/SW=1):connecttoDGNDorDVDD. ThestandbymodecanbeactivatedusingCONFIGbitC25(STBY). 8 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8528 ADS8548 ADS8568 ADS8528,ADS8548,ADS8568 www.ti.com SBAS543C–AUGUST2011–REVISEDFEBRUARY2016 7 Specifications 7.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT HVDDtoAGND –0.3 18 HVSStoAGND –18 0.3 Supplyvoltage V AVDDtoAGND –0.3 6 DVDDtoDGND –0.3 6 Analoginputvoltage HVSS–0.3 HVDD+0.3 V ReferenceinputvoltagewithrespecttoAGND AGND–0.3 AVDD+0.3 V DigitalinputvoltagewithrespecttoDGND DGND–0.3 DVDD+0.3 V GroundvoltagedifferenceAGNDtoDGND ±0.3 V Inputcurrenttoallpinsexceptsupply ±10 mA Maximumvirtualjunctiontemperature,T 150 °C J Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 7.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2500 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT AVDD Analogsupplyvoltage 4.5 5.0 5.5 V DVDD BufferI/Osupplyvoltage 2.7 3.3 5.5 V HVDD Inputpositivesupplyvoltage 5.0 15.0 16.5 V HVSS Inputnegativesupplyvoltage –16.5 –15.0 –5.0 V T Operatingambienttemperaturerange –40 25 125 °C A 7.4 Thermal Information ADS85x8 THERMALMETRIC(1) RGC(VQFN) PM(LQFP) UNIT 64PINS 64PINS R Junction-to-ambientthermalresistance 22 48.5 °C/W θJA R Junction-to-case(top)thermalresistance 9.0 9.4 °C/W θJC(top) R Junction-to-boardthermalresistance 3.6 21.9 °C/W θJB ψ Junction-to-topcharacterizationparameter 0.1 0.3 °C/W JT ψ Junction-to-boardcharacterizationparameter 2.9 21.4 °C/W JB R Junction-to-case(bottom)thermalresistance 0.3 n/a °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:ADS8528 ADS8548 ADS8568 ADS8528,ADS8548,ADS8568 SBAS543C–AUGUST2011–REVISEDFEBRUARY2016 www.ti.com 7.5 Electrical Characteristics: General AllminimumandmaximumspecificationsareatT =–40°Cto+125°C,specifiedsupplyvoltagerange,VREF=2.5V A (internal),V =±10V,andf =max,unlessotherwisenoted.TypicalvaluesareatT =25°C,HVDD=15V,HVSS= IN DATA A –15V,AVDD=5V,andDVDD=3.3V. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT ANALOGINPUT RANGEpin,RANGEbit=0 –4VREF 4VREF CHXX Bipolarfull-scalerange V RANGEpin,RANGEbit=1 –2VREF 2VREF Inputrange=±4VREF 10 Inputcapacitance pF Inputrange=±2VREF 20 Inputleakagecurrent Noongoingconversion –1 1 μA Aperturedelay 5 ns Aperturedelaymatching CommonCONVSTforallchannels 100 ps Aperturejitter 50 ps PSRR Power-supplyrejectionratio AtoutputcodeFFFFh,relatedtoHVDDandHVSS –78 dB REFERENCEVOLTAGEOUTPUT(REFOUT) 2.5-Voperation,REFDAC=3FFh 2.485 2.5 2.515 2.5-Voperation,REFDAC=3FFhat25°C 2.496 2.5 2.504 VREF Referencevoltage V 3.0-Voperation,REFDAC=3FFh 2.985 3.0 3.015 3.0-Voperation,REFDAC=3FFhat25°C 2.995 3.0 3.005 dVREF/dT Referencevoltagedrift ±10 ppm/°C PSRR Power-supplyrejectionratio AtoutputcodeFFFFh,relatedtoAVDD –77 dB IREFOUT Outputcurrent Atdccurrent –2 2 mA IREFSC Short-circuitcurrent(1) 50 mA tREFON Turn-onsettlingtime 10 ms AtREF_xP,REF_xNpins 4.7 10 μF Externalloadcapacitance AtREFIOpin 100 470 nF REFDAC Tuningrange Internalreferenceoutputvoltagerange 0.2VREF VREF V REFDACresolution 10 Bits DNLDAC REFDACdifferentialnonlinearity –1 ±0.1 1 LSB INLDAC REFDACintegralnonlinearity –2 ±0.1 2 LSB VOSDAC REFDACoffseterror VREF=0.5V(DAC=0CDh) –4 ±0.65 4 LSB REFERENCEVOLTAGEINPUT(REFIN) VREFIN Referenceinputvoltage 0.5 2.5 3.025 V Inputresistance 100 MΩ Inputcapacitance 5 pF Referenceinputcurrent 1 μA DIGITALINPUTS(2)(CMOSwithSchmitt-TriggerLogicFamily) DVDD+ High-levelinputvoltage 0.7DVDD V 0.3 DGND– Low-levelinputvoltage 0.3DVDD V 0.3 Inputcurrent VI=DVDDtoDGND –50 50 nA Inputcapacitance 5 pF DIGITALOUTPUTS(2) Outputcapacitance 5 pF Loadcapacitance 30 pF High-impedance-stateoutputcurrent –50 50 nA Logicfamily CMOS DVDD– VOH High-leveloutputvoltage IOH=100μA 0.6 V DGND+ VOL Low-leveloutputvoltage IOH=–100μA 0.4 V (1) Referenceoutputcurrentisnotlimitedinternally. (2) Specifiedbydesign. 10 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:ADS8528 ADS8548 ADS8568
Description:The list of books you might like
