11-Bit, 200 MSPS ADC

55 Pages·2014·1.76 MB·English

ADS5517
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SLWS203–DECEMBER2007
11-BIT, 200 MSPS ADC
FEATURES • ClockDutyCycleStabilizer
1
• MaximumSampleRate:200MSPS • NoExternal ReferenceDecouplingRequired
• 11-BitResolution • InternalandExternal ReferenceSupport
• NoMissingCodes • ProgrammableOutput ClockPositiontoEase
• TotalPower Dissipation1.23W DataCapture
• InternalSampleand Hold • 3.3-VAnalog andDigitalSupply
• 67-dBFSSNRat70-MHzIF • 48-QFNPackage(7mm· 7mm)
• 84-dBcSFDRat70-MHzIF, 0-dBGain
APPLICATIONS
• HighAnalogBandwidthupto800MHz
• WirelessCommunicationsInfrastructure
• DoubleDataRate(DDR)LVDSandParallel
• SoftwareDefinedRadio
CMOSOutputOptions
• PowerAmplifier Linearization
• ProgrammableGainupto6dB forSNR/SFDR
• 802.16d/e
Trade-OffatHighIF
• TestandMeasurement Instrumentation
• ReducedPower ModesatLowerSampleRates
• HighDefinitionVideo
• SupportsInputClockAmplitudeDownto • Medical Imaging
400mV
PP • RadarSystems
In a compact 48-pin QFN, the device offers fully
DESCRIPTION differential LVDS DDR (Double Data Rate) interface
while parallel CMOS outputs can also be selected.
ADS5517 is a high performance 11-bit, 200-MSPS Flexible output clock position programmability is
A/D converter. It offers state-of-the art functionality available to ease capture and trade-off setup for hold
and performance using advanced techniques to times. At lower sampling rates, the ADC can be
minimize board space. With high analog bandwidth operated at scaled down power with no loss in
and low jitter input clock buffer, the ADC supports performance. The ADS5517 includes an internal
both high SNR and high SFDR at high input reference, while eliminating the traditional reference
frequencies. It features programmable gain options pins and associated external decoupling. The device
that can be used to improve SFDR performance at alsosupportsanexternalreferencemode.
lowerfull-scaleanaloginputranges.
The device is specified over the industrial
temperaturerange(-40(cid:176) Cto85(cid:176) C).
ADS5517PRODUCTFAMILY
210MSPS 190MSPS 170MSPS
14bit ADS5547 ADS5546 ADS5545
12bit ADS5527 - ADS5525
ADS5517
11bit
(200MSPS)
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof
TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2007,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
ADS5517
www.ti.com
SLWS203–DECEMBER2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore
susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
D D
D D D N
D N V G
V G R R
A A D D
CLKP CLKOUTP
CLOCKGEN
CLKM CLKOUTM
LOW_D0_P
LOW_D0_M
D1_D2_P
D1_D2_M
D3_D4_P
D3_D4_M
INP Digital
11-Bit Encoder D5_D6_P
SHA
ADC and
D5_D6_M
INM Serializer
D7_D8_P
D7_D8_M
D9_D10_P
D9_D10_M
Control
VCM Reference
Interface
OVR
F K N A T E S E
RE CL SE AT SE O DF OD LVDS MODE
I S SD RE M
PACKAGE/ORDERINGINFORMATION(1)
SPECIFIED TRANSPORT
PACKAGE- PACKAGE PACKAGE ORDERING
PRODUCT TEMPERATURE MEDIA,
LEAD DESIGNATOR MARKING NUMBER
RANGE QUANTITY
TapeandReel,
ADS5517IRGZT
250
ADS5517 QFN-48(2) RGZ –40(cid:176) Cto85(cid:176) C AZ5517
TapeandReel,
ADS5517IRGZR
2500
(1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI
websiteatwww.ti.com.
(2) Forthermalpadsizeonthepackage,seethemechanicaldrawingsattheendofthisdatasheet.q =25.41(cid:176) C/W(0LFMairflow),
JA
q =16.5(cid:176) C/Wwhenusedwith2oz.coppertraceandpadsoldereddirectlytoaJEDECstandardfourlayer3inx3in(7.62cmx7.62
JC
cm)PCB.
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ABSOLUTE MAXIMUM RATINGS(1)
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
VALUE UNIT
Supplyvoltagerange,AVDD –0.3to3.9 V
Supplyvoltagerange,DRVDD –0.3to3.9 V
VoltagebetweenAGNDandDRGND -0.3to0.3 V
VoltagebetweenAVDDtoDRVDD -0.3to3.3 V
VoltageappliedtoVCMpin(inexternalreferencemode) -0.3to1.8 V
Voltageappliedtoanaloginputpins,INPandINM –0.3tominimum(3.6,AVDD+0.3) V
Voltageappliedtoinputclockpins,CLKPandCLKM -0.3toAVDD+0.3 V
T Operatingfree-airtemperaturerange –40to85 (cid:176) C
A
T Operatingjunctiontemperaturerange 125 (cid:176) C
J
T Storagetemperaturerange –65to150 (cid:176) C
stg
(1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings
onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating
conditionsisnotimplied.Exposuretoabsolutemaximumratedconditionsforextendedperiodsmayaffectdevicereliability.
RECOMMENDED OPERATING CONDITIONS
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
MIN TYP MAX UNIT
SUPPLIES
Analogsupplyvoltage,AVDD 3 3.3 3.6 V
Digitalsupplyvoltage,DRVDD 3 3.3 3.6 V
ANALOGINPUTS
Differentialinputvoltagerange 2 V
PP
Inputcommon-modevoltage 1.5±0.1 V
VoltageappliedonVCMinexternalreferencemode 1.45 1.5 1.55 V
CLOCKINPUT
Inputclocksamplerate (1) MSPS
DEFAULTSPEEDmode 50 200
MSPS
LOWSPEEDmode 1 60
Inputclockamplitudedifferential(V -V )
(CLKP) (CLKM)
Sinewave,ac-coupled 0.4 1.5 V
PP
LVPECL,ac-coupled 1.6 V
PP
LVDS,ac-coupled 0.7 V
PP
LVCMOS,single-ended,ac-coupled 3.3 V
Inputclockdutycycle(SeeFigure25) 35% 50% 65%
DIGITALOUTPUTS
C MaximumexternalloadcapacitancefromeachoutputpintoDRGND(LVDSandCMOSmodes)
L
Withoutinternaltermination(defaultafterreset) 5 pF
With100Ωinternaltermination (2) 10 pF
R DifferentialloadresistancebetweentheLVDSoutputpairs(LVDSmode) 100 Ω
L
Operatingfree-airtemperature –40 85 (cid:176) C
(1) SeethesectiononLowSamplingFrequencyOperationformoreinformation.
(2) SeethesectiononLVDSBufferInternalterminationformoreinformation.
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ELECTRICAL CHARACTERISTICS
Typicalvaluesareat25(cid:176) C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40(cid:176) CtoT =85(cid:176) C,
MIN MAX
AVDD=DRVDD=3.3V,samplingrate=200MSPS,sinewaveinputclock,1.5V differentialclockamplitude,50%clock
PP
dutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,0-dbgain,DDRLVDSdataoutput(unlessotherwise
noted)
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
Resolution 11 bits
ANALOGINPUT
Differentialinputvoltagerange 2 V
PP
Differentialinputcapacitance 7 pF
Analoginputbandwidth 800 MHz
Analoginputcommonmodecurrent 342 m A
(perinputpin)
REFERENCEVOLTAGES
V Internalreferencebottomvoltage Internalreferencemode 0.5 V
(REFB)
V Internalreferencetopvoltage Internalreferencemode 2.5 V
(REFT)
ΔV Internalreferenceerror V -V -60 ±25 60 mV
(REF) (REFT) (REFB)
V Commonmodeoutputvoltage Internalreferencemode 1.5 V
CM
VCMoutputcurrentcapability Internalreferencemode ±4 mA
DCACCURACY
NoMissingCodes Specified
DNL Differentialnon-linearity -0.6 ±0.3 1.0 LSB
INL Integralnon-linearity -1.5 ±0.6 1.5 LSB
Offseterror -10 5 10 mV
Offsettemperaturecoefficient 0.002 ppm/(cid:176) C
Gainerrorduetointernalreference (ΔV /2.0V)% -3 ±1 3 %FS
(REF)
erroralone
Gainerrorexcludinginternalreference -2 ±1 2 %FS
error(1)
Gaintemperaturecoefficient 0.01 Δ%/(cid:176) C
PSRR DCPowersupplyrejectionratio 0.6 mV/V
POWERSUPPLY
I Analogsupplycurrent 306 mA
(AVDD)
LVDSmode,I =3.5mA,
O 66 mA
R =100Ω,C =5pF
L L
I Digitalsupplycurrent
(DRVDD)
CMOSmode,F =2.5MHz,
IN 47 mA
C =5pF
L
I Totalsupplycurrent LVDSmode 372 mA
CC
Totalpowerdissipation LVDSmode 1.23 1.4 W
Standbypower InSTANDBYmodewithclockstopped 100 150 mW
Clockstoppower Withinputclockstopped 100 150 mW
(1) Gainerrorisspecifiedfromdesignandcharacterization;itisnottestedinproduction.
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ELECTRICAL CHARACTERISTICS
Typicalvaluesareat25(cid:176) C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40(cid:176) CtoT =85(cid:176) C,
MIN MAX
AVDD=DRVDD=3.3V,samplingrate=200MSPS,sinewaveinputclock,1.5V differentialclockamplitude,50%clock
PP
dutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,0-dbgain,DDRLVDSdataoutput(unlessotherwise
noted)
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
ACCHARACTERISTICS
F =20MHz 67.1
IN
F =70MHz 64.5 66.9
IN
F =100MHz 66.8
IN
F =170MHz 66.6
IN
SNR Signaltonoiseratio dBFS
0dBgain,2V FS(1) 66
PP
F =230MHz
IN
3dBgain,1.4V FS 65.4
PP
0dBgain,2V FS 65
PP
F =400MHz
IN
3dBgain,1.4V FS 64.5
PP
F =20MHz 86
IN
F =70MHz 75 84
IN
F =100MHz 78
IN
F =170MHz 79
IN
0dBgain,2V FS 75
PP
SFDR Spuriousfreedynamicrange F =230MHz dBc
IN
3dBgain,1.4V FS 78
PP
0dBgain,2V FS 74
PP
F =300MHz
IN
3dBgain,1.4V FS 76
PP
0dBgain,2V FS 68
PP
F =400MHz
IN
3dBgain,1.4V FS 70
PP
F =20MHz 67
IN
F =70MHz 64 66.8
IN
F =100MHz 66.6
IN
F =170MHz 66.4
IN
SINAD Signaltonoiseanddistortionratio dBFS
0dBgain,2V FS 65
PP
F =230MHz
IN
3dBgain,1.4V FS 65
PP
0dBgain,2V FS 62.8
PP
F =400MHz
IN
3dBgain,1.4V FS 62.9
PP
F =20MHz 91
IN
F =70MHz 75 88
IN
F =100MHz 87
IN
F =170MHz 87
IN
0dBgain,2V FS 86
PP
HD2 Secondharmonic F =230MHz dBc
IN
3dBgain,1.4V FS 88
PP
0dBgain,2V FS 78
PP
F =300MHz
IN
3dBgain,1.4V FS 80
PP
0dBgain,2V FS 69
PP
F =400MHz
IN
3dBgain,1.4V FS 71
PP
(1) FS=Fullscalerange
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ELECTRICAL CHARACTERISTICS (continued)
Typicalvaluesareat25(cid:176) C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40(cid:176) CtoT =85(cid:176) C,
MIN MAX
AVDD=DRVDD=3.3V,samplingrate=200MSPS,sinewaveinputclock,1.5V differentialclockamplitude,50%clock
PP
dutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,0-dbgain,DDRLVDSdataoutput(unlessotherwise
noted)
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
F =20MHz 86
IN
F =70MHz 75 84
IN
F =100MHz 78
IN
F =170MHz 79
IN
0dBgain,2V FS 75
PP
HD3 Thirdharmonic F =230MHz dBc
IN
3dBgain,1.4V FS 78
PP
0dBgain,2V FS 74
PP
F =300MHz
IN
3dBgain,1.4V FS 76
PP
0dBgain,2V FS 68
PP
F =400MHz
IN
3dBgain,1.4V FS 70
PP
F =20MHz 95
IN
F =70MHz 92
IN
F =100MHz 92
IN
Worstharmonic(otherthanHD2,HD3) F =170MHz 90 dBc
IN
F =230MHz 90
IN
F =300MHz 88
IN
F =400MHz 87
IN
F =20MHz 83
IN
F =70MHz 73 82
IN
F =100MHz 76
IN
THD Totalharmonicdistortion F =170MHz 77 dBc
IN
F =230MHz 73
IN
F =300MHz 72
IN
F =400MHz 65
IN
ENOB Effectivenumberofbits F =70MHz 10.3 10.8 bits
IN
F =50.03MHz,F =46.03MHz, 91
IN1 IN2
-7dBFSeachtone
IMD Two-toneintermodulationdistortion dBFS
F =190.1MHz,F =185.02MHz,
IN1 IN2 86
-7dBFSeachtone
PSRR ACpowersupplyrejectionratio 30MHz,200mV signalon3.3-Vsupply 35 dBc
PP
Recoveryto1%(offinalvalue)for6-dBoverload Clock
Voltageoverloadrecoverytime 1
withsine-waveinputatNyquistfrequency cycles
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DIGITAL CHARACTERISTICS(1)
TheDCspecificationsrefertotheconditionwherethedigitaloutputsarenotswitching,butarepermanentlyatavalidlogic
level0or1AVDD=DRVDD=3.3V,I =3.5mA,R =100Ω (2)
O L
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
DIGITALINPUTS
High-levelinputvoltage 2.4 V
Low-levelinputvoltage 0.8 V
High-levelinputcurrent 33 m A
Low-levelinputcurrent –33 m A
Inputcapacitance 4 pF
DIGITALOUTPUTS–CMOSMODE
High-leveloutputvoltage 3.3 V
Low-leveloutputvoltage 0 V
Outputcapacitance Outputcapacitanceinsidethedevice,fromeachoutputto 2 pF
ground
DIGITALOUTPUTS–LVDSMODE
High-leveloutputvoltage 1375 mV
Low-leveloutputvoltage 1025 mV
Outputdifferentialvoltage,|V | 225 350 425 mV
OD
V Outputoffsetvoltage,single-ended Common-modevoltageofOUTPandOUTM 1200 mV
OS
Outputcapacitanceinsidethedevice,fromeitheroutputto
Outputcapacitance 2 pF
ground
(1) AllLVDSandCMOSspecificationsarecharacterized,butnottestedatproduction.
(2) I referstotheLVDSbuffercurrentsetting,R isthedifferentialloadresistancebetweentheLVDSoutputpair.
O L
TIMING CHARACTERISTICS – LVDS AND CMOS MODES(1)
Typicalvaluesareat25(cid:176) C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40(cid:176) CtoT =85(cid:176) C,AVDD=
MIN MAX
DRVDD=3.3V,samplingfrequency=200MSPS,sinewaveinputclock,1.5V clockamplitude,C =5pF(2),I =3.5mA,
PP L O
R =100Ω (3),nointernaltermination,unlessotherwisenoted.
L
Fortimingsatlowersamplingfrequencies,seetheOutputTimingsectionintheAPPLICATIONINFORMATIONofthisdata
sheet.
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
t Aperturedelay 1.2 ns
a
t Aperturejitter 150 fsrms
j
Timetovaliddataaftercomingoutof
100
STANDBYmode
Wake-uptime m s
Timetovaliddataafterstoppingand
100
restartingtheinputclock
clock
Latency 14
cycles
DDRLVDSMODE(4)
t Datasetuptime(5) Datavalid (6)tozero-crossofCLKOUTP 1.0 1.5 ns
su
th Dataholdtime(5) Zinevraol-idcr(6o)ssofCLKOUTPtodatabecoming 0.35 0.8 ns
(1) Timingparametersarespecifiedbydesignandcharacterizationandnottestedinproduction.
(2) C istheeffectiveexternalsingle-endedloadcapacitancebetweeneachoutputpinandground.
L
(3) I referstotheLVDSbuffercurrentsetting;R isthedifferentialloadresistancebetweentheLVDSoutputpair.
O L
(4) Measurementsaredonewithatransmissionlineof100Ωcharacteristicimpedancebetweenthedeviceandtheload.
(5) Setupandholdtimespecificationstakeintoaccounttheeffectofjitterontheoutputdataandclock.Thesespecificationsalsoassume
thatthedataandclockpathsareperfectlymatchedwithinthereceiver.Anymismatchinthesepathswithinthereceiverwouldappear
asreducedtimingmargin.
(6) Datavalidreferstologichighof+50mVandlogiclowof–50mV.
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TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)
Fortimingsatlowersamplingfrequencies,seetheOutputTimingsectionintheAPPLICATIONINFORMATIONofthisdata
sheet.
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
t Clockpropagationdelay(7) Inputclockrisingedgezero-crosstooutput 3.7 4.4 5.1 ns
PDI clockrisingedgezero-cross
Dutycycleofdifferentialclock,
LVDSbitclockdutycycle (CLKOUTP-CLKOUTM) 45% 50% 55%
80≤Fs≤200MSPS
Risetimemeasuredfrom–50mVto50
t , Datarisetime, mV
r 50 100 200 ps
t Datafalltime Falltimemeasuredfrom50mVto–50mV
f
1≤Fs≤200MSPS
Risetimemeasuredfrom–50mVto50
t , Outputclockrisetime, mV
CLKRISE 50 100 200 ps
t Outputclockfalltime Falltimemeasuredfrom50mVto–50mV
CLKFALL
1≤Fs≤200MSPS
Outputclockjitter Cycle-to-cyclejitter 120 pspp
t Outputenable(OE)tovaliddata TimetovaliddataafterOEbecomes 1 m s
OE delay active
PARALLELCMOSMODE
t Datasetuptime (5) Datavalid(8)to50%ofCLKOUTrising 1.8 2.6 ns
su edge
th Dataholdtime (5) 5b0e%comofinCgLiKnOvaUliTd(r8i)singedgetodata 0.4 0.8 ns
t Clockpropagationdelay(7) Inputclockrisingedgezero-crossto50% 2.6 3.4 4.2 ns
PDI ofCLKOUTrisingedge
Dutycycleofoutputclock(CLKOUT)
Outputclockdutycycle 45%
80≤Fs≤200MSPS
Risetimemeasuredfrom20%to80%of
DRVDD
t , Datarisetime,
r Falltimemeasuredfrom80%to20%of 0.8 1.5 2.0 ns
t Datafalltime
f DRVDD
1≤Fs≤200MSPS
Risetimemeasuredfrom20%to80%of
DRVDD
t , Outputclockrisetime,
CLKRISE Falltimemeasuredfrom80%to20%of 0.4 0.8 1.2 ns
t Outputclockfalltime
CLKFALL DRVDD
1≤Fs≤200MSPS
Outputenable(OE)tovaliddata TimetovaliddataafterOEbecomes
t 50 ns
OE delay active
(7) Tousetheinputclockasthedatacaptureclock,itisnecessarytodelaytheinputclockbyadelay(t )togetthedesiredsetupandhold
D
times.Useeitheroftheseequationstocalculatet :
D
Desiredsetuptime=t -(t -t )
D PDI su
Desiredholdtime=(t +t )-t
PDI h D
(8) Datavalidreferstologichighof2Vandlogiclowof0.8V
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N+3 N+4 N+16 N+17
N+2 N+15
Sample N+1 N+14
N
Input
Signal
t
a
CLKP
Input
Clock
CLKM
CLKOUTM
CLKOUTP
t
su
t
14 Clock Cycles th PDI
DDR
LVDS
Output Data
O E O E O E O E O E O E O E O E O E O E
DXP, DXM
E–Even Bits D0,D2,D4,D6,D8,D10 N–14 N–13 N–12 N–11 N–10 N–1 N N+1 N+2
O–Odd Bits D1,D3,D5,D7,D9
t
PDI
CLKOUT
t
su
Parallel
CMOS 14 Clock Cycles th
Output Data
N–14 N–13 N–12 N–11 N–10 N–1 N N+1 N+2
D0–D10
Figure1.Latency
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CLKM
Input
Clock
CLKP
t
PDI
CLKOUTP
Output
Clock
CLKOUTM
t t
h su
t t
su h
Output Dn_Dn+1_P, (NoteA) (NoteB)
Dn Dn+1
Data Pair Dn_Dn+1_M
A. Dn–BitsD1,D3,D5,D7,andD9
B. Dn+1–BitsD0,D2,D4,D6,D8,andD10
Figure2. LVDSModeTiming
CLKM
Input
Clock
CLKP
t
PDI
Output
CLKOUT
Clock
t
h
t
su
Output (NoteA)
Dn Dn
Data
A. Dn–BitsD0–D10
Figure3.CMOSModeTiming
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