1076-2000 IEEE Standard VHDL Language Reference Manual

299 Pages·2000·1.458 MB·

IEEE Std 1076, 2000 Edition
(Incorporates IEEE Std 1076-1993
and IEEE Std 1076a-2000)
IEEE Standard VHDL
Language Reference Manual
Cosponsors
Design Automation Standards Committee (DASC)
of the
IEEE Computer Society
and
Automatic Test Program Generation Subcommittee
of the
IEEE Standards Coordinating Committee 20 (SCC 20)
Approved 30 January 2000
IEEE-SA Standards Board
Abstract: VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation
intended for use in all phases of the creation of electronic systems. Because it is both machine read-
able and human readable, it supports the development, verification, synthesis, and testing of hard-
ware designs; the communication of hardware design data; and the maintenance, modification, and
procurement of hardware. Its primary audiences are the implementors of tools supporting the lan-
guage and the advanced users of the language.
Keywords: computer languages, electronic systems, hardware, hardware design, VHDL
The Institute of Electrical and Electronics Engineers, Inc.
3 Park Avenue, New York, NY 10016-5997, USA
Copyright © 2000 by the Institute of Electrical and Electronics Engineers, Inc.
All rights reserved. Published 29 December 2000. Printed in the United States of America.
Print: ISBN 0-7381-1948-2 SH94817
PDF: ISBN 0-7381-1949-0 SS94817
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Introduction
(This introduction is not part of IEEE Std 1076, 2000 Edition, IEEE Standards VHDL Language Reference Manual.)
The VHSIC Hardware Description Language (VHDL) is a formal notation intended for use in all phases of
the creation of electronic systems. Because it is both machine readable and human readable, it supports the
development, verification, synthesis, and testing of hardware designs; the communication of hardware
design data; and the maintenance, modification, and procurement of hardware.
This document specifies IEEE Std 1076, 2000 Edition, which incorporates IEEE Std 1076-1993 and IEEE
Std 1076a-2000.
Participants
The following individuals participated in the development of this standard:
Stephen A. Bailey, Chair
Peter J. Ashenden Serge Maginot Gregory D. Peterson
David L. Barton Paul J. Menchini Jacques Rouillard
Victor Berman Jean Mermet Ron Werner
Alain Fonkoua Rob Newshutz John Willis
Andrew Guyler William R. Paulsen Phil Wilsey
John Hillawi Alex Zamfirescu
The following members of the balloting committee voted on this standard:
Peter J. Ashenden Rich Hatcher Gregory D. Peterson
Stephen A. Bailey Carl E. Hein Markus Pfaff
David L. Barton John Hillawi Steffen Rochel
Victor Berman John Hines Jacques Rouillard
J. Bhasker Osamu Karatsu Quentin G. Schmierer
Dominique Borrione Jake Karrfalt Steven E. Schulz
Todd P. Carpenter Michael D. McKinney Moe Shahdad
Allen Dewey Paul J. Menchini Charles F. Shelor
Douglas D. Dunlop John T. Montague Hiroshi Shinkai
Wayne P. Fischer Gabe Moretti Joseph J. Stanco
Rita A. Glover Gerald Musgrave Atsushi Takahara
Kenji Goto Zainalabedin Navabi David Tester
Brian S. Griffin Kevin O’Brien Peter Trajmar
Andrew Guyler Serafin Olcoz J. Richard Weger
M. M. Kamal Hashmi Vincent Olive John Willis
Copyright © 2000 IEEE. All rights reserved. iii
When the IEEE-SA Standards Board approved this standard on 30 January 2000, it had the following
membership:
Richard J. Holleman, Chair
Donald N. Heirman, Vice Chair
Judith Gorman, Secretary
Satish K. Aggarwal James H. Gurney Louis-François Pau
Dennis Bodson Lowell G. Johnson Ronald C. Petersen
Mark D. Bowman Robert J. Kennelly Gerald H. Peterson
James T. Carlo E. G. “Al” Kiener John B. Posey
Gary R. Engmann Joseph L. Koepfinger* Gary S. Robinson
Harold E. Epstein L. Bruce McClung Akio Tojo
Jay Forster* Daleep C. Mohla Hans E. Weinrich
Ruben D. Garzon Robert F. Munzner Donald W. Zipse
*Member Emeritus
Also included is the following nonvoting IEEE-SA Standards Board liaison:
Robert E. Hebner
Andrew D. Ickowicz
IEEE Standards Project Editor
iv Copyright © 2000 IEEE. All rights reserved.
Contents
0. Overview of this standard....................................................................................................................1
0.1 Intent and scope of this standard..................................................................................................1
0.2 Structure and terminology of this standard..................................................................................1
0.2.1 Syntactic description................................................................................................................. 2
0.2.2 Semantic description .................................................................................................................3
0.2.3 Front matter, examples, notes, references, and annexes ...........................................................3
1. Design entities and configurations.......................................................................................................5
1.1 Entity declarations.......................................................................................................................5
1.1.1 Entity header .............................................................................................................................5
1.1.1.1 Generics .................................................................................................................................6
1.1.1.2 Ports .......................................................................................................................................7
1.1.2 Entity declarative part ...............................................................................................................8
1.1.3 Entity statement part .................................................................................................................9
1.2 Architecture bodies......................................................................................................................9
1.2.1 Architecture declarative part ...................................................................................................10
1.2.2 Architecture statement part .....................................................................................................10
1.3 Configuration declarations.........................................................................................................12
1.3.1 Block configuration ................................................................................................................13
1.3.2 Component configuration .......................................................................................................15
2. Subprograms and packages................................................................................................................19
2.1 Subprogram declarations...........................................................................................................19
2.1.1 Formal parameters ..................................................................................................................20
2.1.1.1 Constant and variable parameters........................................................................................ 20
2.1.1.2 Signal parameter ..................................................................................................................21
2.1.1.3 File parameters .....................................................................................................................22
2.2 Subprogram bodies....................................................................................................................22
2.3 Subprogram overloading............................................................................................................25
2.3.1 Operator overloading ..............................................................................................................26
2.3.2 Signatures ................................................................................................................................26
2.4 Resolution functions..................................................................................................................27
2.5 Package declarations..................................................................................................................28
2.6 Package bodies...........................................................................................................................29
2.7 Conformance rules.....................................................................................................................31
3. Types..................................................................................................................................................33
3.1 Scalar types................................................................................................................................34
3.1.1 Enumeration types ..................................................................................................................34
3.1.1.1 Predefined enumeration types ..............................................................................................35
3.1.2 Integer types ............................................................................................................................36
3.1.2.1 Predefined integer types .......................................................................................................36
3.1.3 Physical types ..........................................................................................................................36
3.1.3.1 Predefined physical types ....................................................................................................38
3.1.4 Floating point types .................................................................................................................39
3.1.4.1 Predefined floating point types ............................................................................................40
3.2 Composite types.........................................................................................................................40
Copyright © 2000 IEEE. All rights reserved. v
3.2.1 Array types ..............................................................................................................................40
3.2.1.1 Index constraints and discrete ranges ..................................................................................42
3.2.1.2 Predefined array types ..........................................................................................................44
3.2.2 Record types ............................................................................................................................44
3.3 Access types...............................................................................................................................45
3.3.1 Incomplete type declarations ..................................................................................................46
3.3.2 Allocation and deallocation of objects ....................................................................................47
3.4 File types....................................................................................................................................47
3.4.1 File operations .........................................................................................................................48
3.5 Protected types...........................................................................................................................50
3.5.1 Protected type declarations .....................................................................................................50
3.5.2 Protected type bodies ..............................................................................................................51
4. Declarations.......................................................................................................................................55
4.1 Type declarations.......................................................................................................................55
4.2 Subtype declarations..................................................................................................................56
4.3 Objects.......................................................................................................................................57
4.3.1 Object declarations ..................................................................................................................58
4.3.1.1 Constant declarations ...........................................................................................................58
4.3.1.2 Signal declarations ...............................................................................................................59
4.3.1.3 Variable declarations ...........................................................................................................60
4.3.1.4 File declarations ...................................................................................................................62
4.3.2 Interface declarations ..............................................................................................................63
4.3.2.1 Interface lists ........................................................................................................................65
4.3.2.2 Association lists ...................................................................................................................66
4.3.3 Alias declarations ....................................................................................................................68
4.3.3.1 Object aliases .......................................................................................................................69
4.3.3.2 Nonobject aliases .................................................................................................................70
4.4 Attribute declarations.................................................................................................................71
4.5 Component declarations.............................................................................................................72
4.6 Group template declarations......................................................................................................72
4.7 Group declarations.....................................................................................................................73
5. Specifications.....................................................................................................................................75
5.1 Attribute specification................................................................................................................75
5.2 Configuration specification........................................................................................................77
5.2.1 Binding indication ...................................................................................................................78
5.2.1.1 Entity aspect .........................................................................................................................80
5.2.1.2 Generic map and port map aspects ......................................................................................81
5.2.2 Default binding indication ......................................................................................................83
5.3 Disconnection specification.......................................................................................................84
6. Names................................................................................................................................................87
6.1 Names........................................................................................................................................87
6.2 Simple names.............................................................................................................................88
6.3 Selected names...........................................................................................................................89
6.4 Indexed names...........................................................................................................................91
6.5 Slice names................................................................................................................................92
6.6 Attribute names..........................................................................................................................92
vi Copyright © 2000 IEEE. All rights reserved.
7. Expressions........................................................................................................................................95
7.1 Rules for expressions.................................................................................................................95
7.2 Operators....................................................................................................................................96
7.2.1 Logical operators ....................................................................................................................96
7.2.2 Relational operators ................................................................................................................97
7.2.3 Shift operators .........................................................................................................................98
7.2.4 Adding operators ...................................................................................................................100
7.2.5 Sign operators .......................................................................................................................102
7.2.6 Multiplying operators ............................................................................................................102
7.2.7 Miscellaneous operators ........................................................................................................104
7.3 Operands..................................................................................................................................104
7.3.1 Literals ..................................................................................................................................105
7.3.2 Aggregates .............................................................................................................................106
7.3.2.1 Record aggregates ..............................................................................................................106
7.3.2.2 Array aggregates ................................................................................................................107
7.3.3 Function calls ........................................................................................................................108
7.3.4 Qualified expressions ............................................................................................................108
7.3.5 Type conversions ..................................................................................................................109
7.3.6 Allocators ..............................................................................................................................110
7.4 Static expressions.....................................................................................................................111
7.4.1 Locally static primaries .........................................................................................................111
7.4.2 Globally static primaries .......................................................................................................112
7.5 Universal expressions..............................................................................................................113
8. Sequential statements.......................................................................................................................115
8.1 Wait statement.........................................................................................................................115
8.2 Assertion statement..................................................................................................................117
8.3 Report statement......................................................................................................................118
8.4 Signal assignment statement....................................................................................................118
8.4.1 Updating a projected output waveform .................................................................................120
8.5 Variable assignment statement................................................................................................123
8.5.1 Array variable assignments................................................................................................... 124
8.6 Procedure call statement..........................................................................................................124
8.7 If statement...............................................................................................................................125
8.8 Case statement.........................................................................................................................125
8.9 Loop statement.........................................................................................................................126
8.10Next statement.........................................................................................................................127
8.11Exit statement...........................................................................................................................127
8.12Return statement......................................................................................................................128
8.13Null statement..........................................................................................................................128
9. Concurrent statements......................................................................................................................129
9.1 Block statement........................................................................................................................129
9.2 Process statement.....................................................................................................................130
9.3 Concurrent procedure call statements......................................................................................131
9.4 Concurrent assertion statements..............................................................................................132
9.5 Concurrent signal assignment statements................................................................................133
9.5.1 Conditional signal assignments .............................................................................................135
9.5.2 Selected signal assignments ..................................................................................................137
9.6 Component instantiation statements........................................................................................138
9.6.1 Instantiation of a component .................................................................................................139
Copyright © 2000 IEEE. All rights reserved. vii
9.6.2 Instantiation of a design entity ..............................................................................................141
9.7 Generate statements.................................................................................................................144
10. Scope and visibility..........................................................................................................................145
10.1Declarative region....................................................................................................................145
10.2Scope of declarations...............................................................................................................145
10.3Visibility..................................................................................................................................146
10.4Use clauses...............................................................................................................................150
10.5The context of overload resolution..........................................................................................150
11. Design units and their analysis........................................................................................................153
11.1Design units.............................................................................................................................153
11.2Design libraries........................................................................................................................153
11.3Context clauses........................................................................................................................154
11.4Order of analysis......................................................................................................................155
12. Elaboration and execution................................................................................................................157
12.1Elaboration of a design hierarchy............................................................................................157
12.2Elaboration of a block header..................................................................................................159
12.2.1 The generic clause ...............................................................................................................159
12.2.2 The generic map aspect .......................................................................................................159
12.2.3 The port clause ....................................................................................................................159
12.2.4 The port map aspect ............................................................................................................159
12.3Elaboration of a declarative part..............................................................................................160
12.3.1 Elaboration of a declaration ................................................................................................161
12.3.1.1 Subprogram declarations and bodies ...............................................................................161
12.3.1.2 Type declarations .............................................................................................................161
12.3.1.3 Subtype declarations ........................................................................................................162
12.3.1.4 Object declarations ...........................................................................................................162
12.3.1.5 Alias declarations .............................................................................................................163
12.3.1.6 Attribute declarations .......................................................................................................163
12.3.1.7 Component declarations ...................................................................................................163
12.3.2 Elaboration of a specification .............................................................................................163
12.3.2.1 Attribute specifications ....................................................................................................163
12.3.2.2 Configuration specifications ............................................................................................163
12.3.2.3 Disconnection specifications ...........................................................................................164
12.4Elaboration of a statement part................................................................................................164
12.4.1 Block statements .................................................................................................................164
12.4.2 Generate statements ............................................................................................................164
12.4.3 Component instantiation statements ...................................................................................166
12.4.4 Other concurrent statements ...............................................................................................166
12.5Dynamic elaboration................................................................................................................167
12.6Execution of a model...............................................................................................................167
12.6.1 Drivers .................................................................................................................................168
12.6.2 Propagation of signal values ...............................................................................................168
12.6.3 Updating implicit signals ....................................................................................................171
12.6.4 The simulation cycle ...........................................................................................................172
viii Copyright © 2000 IEEE. All rights reserved.
13. Lexical elements..............................................................................................................................175
13.1Character set.............................................................................................................................175
13.2Lexical elements, separators, and delimiters...........................................................................178
13.3Identifiers.................................................................................................................................179
13.3.1 Basic identifiers ..................................................................................................................179
13.3.2 Extended identifiers ............................................................................................................179
13.4Abstract literals........................................................................................................................179
13.4.1 Decimal literals ...................................................................................................................180
13.4.2 Based literals .......................................................................................................................180
13.5Character literals......................................................................................................................181
13.6String literals............................................................................................................................181
13.7Bit string literals.......................................................................................................................182
13.8Comments................................................................................................................................183
13.9Reserved words........................................................................................................................184
13.10 Allowable replacements of characters...................................................................................185
14. Predefined language environment....................................................................................................187
14.1Predefined attributes................................................................................................................187
14.2Package STANDARD.............................................................................................................201
14.3Package TEXTIO.....................................................................................................................208
Annex A (informative) Syntax Summary....................................................................................................213
Annex B (informative) Glossary..................................................................................................................233
Annex C (informative) Potentially nonportable constructs.........................................................................251
Annex D (informative) Bibliography...........................................................................................................253
Index............................................................................................................................................................255
Copyright © 2000 IEEE. All rights reserved. ix
IEEE Standard VHDL
Language Reference Manual
0. Overview of this standard
This clause describes the purpose and organization of this standard.
0.1 Intent and scope of this standard
The intent of this standard is to define VHSIC Hardware Description Language (VHDL) accurately. Its
primary audiences are the implementor of tools supporting the language and the advanced user of the
language. Other users are encouraged to use commercially available books, tutorials, and classes to learn the
5 language in some detail prior to reading this standard. These resources generally focus on how to use the
language, rather than how a VHDL-compliant tool is required to behave.
At the time of its publication, this document was the authoritative definition of VHDL. From time to time, it
may become necessary to correct and/or clarify portions of this standard. Such corrections and clarifications
may be published in separate documents. Such documents modify this standard at the time of their publica-
10 tion and remain in effect until superseded by subsequent documents or until the standard is officially revised.
0.2 Structure and terminology of this standard
This standard is organized into clauses, each of which focuses on some particular area of the language.
Every fifth line of each clause, not including clause headings, footers, and the clause title, is numbered in the
left margin. Within each clause, individual constructs or concepts are discussed in each subclause.
Each subclause describing a specific construct begins with an introductory paragraph. Next, the syntax of the
15 construct is described using one or more grammatical productions.
A set of paragraphs describing the meaning and restrictions of the construct in narrative form then follow.
Unlike many other IEEE standards, which use the verb shall to indicate mandatory requirements of the stan-
dard and may to indicate optional features, the verb is is used uniformly throughout this document. In all
cases, is is to be interpreted as having mandatory weight.
20 Additionally, the word must is used to indicate mandatory weight. This word is preferred over the more com-
mon shall, as must denotes a different meaning to different readers of this standard.
a) To the developer of tools that process VHDL, must denotes a requirement that the standard imposes.
The resulting implementation is required to enforce the requirement and to issue an error if the
requirement is not met by some VHDL source text.
Copyright © 2000 IEEE. All rights reserved. 1