10-Bit, 200-MSPS, 4-Channel and 12-Bit, 80-MSPS, 8-Channel ADC

107 Pages·2016·2.61 MB·English

ADS5296A
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10-Bit, 200-MSPS, 4-Channel and 12-Bit, 80-MSPS, 8-Channel
Analog-to-Digital Converter
CheckforSamples:ADS5296A
FEATURES DESCRIPTION
1
• ConfigurableModesofOperation: The ADS5296A is a low-power, 12-bit, 8-channel,
2 analog-to-digital converter (ADC) with sample rates
– 10-Bit,200-MSPS,4-ChannelADC
up to 80 MSPS. However, the device can also be
– 12-Bit,160-MSPS,4-ChannelADC configured to operate as a 4-channel ADC running at
– 10-Bit,100-MSPS,8-ChannelADC 2x the sample rate by interleaving data from two ADC
channels. In interleaving mode, the device accepts a
– 12-Bit,80-MSPS,8-ChannelADC
double frequency input clock. Each ADC in a pair
• DesignedforLowPower: converts a common analog input signal at alternate
– 65mWper Channelat80MSPS rising edges of the 2x input clock. The device can
(12-Bit, 8-Channel) either be configured as a 10-bit, 4-channel ADC with
sample rates up to 200 MSPS or as a 12-bit, 4-
– 150mWper Channelat200MSPS
channelADCwithsampleratesupto160MSPS.
(10-Bit, 4-Channel)
The data from each ADC within the interleaved pair is
• 12-Bit,80MSPS:
output in serial format over one LVDS pair up to a
– SNR: 70.3dBFS
maximum data rate of 1 Gbps (10 bits at 100 MSPS).
• 10-Bit,200MSPS: With interleaving disabled, the ADS5296A can also
be operated as an 8-channel, 10-bit device with
– SNR: 61.3dBFS
sampleratesupto100MSPS.
– InterleavingSpur: >60dBcat90MHz
Several digital functions commonly used in systems
• Serial LVDSOne-WireInterface:
are included in the device. These functions include a
– 10xSerializationupto1000MbpsDataRate
low-frequency noise suppression (LFNS) mode,
perWire digital filtering options, and programmable mapping of
– 12xSerializationupto960MbpsDataRate LVDSoutputpinsandanaloginput channels.
perWire
For low input frequency applications, the LFNS mode
• Digital ProcessingBlock: enables the suppression of noise at low frequencies
– ProgrammableFIRDecimationFilterand and improves SNR in the 1-MHz band near dc by
approximately 3 dB. Digital filtering options include
OversamplingtoMinimizeHarmonic
low-pass, high-pass, and band-pass digital filters as
Interference
wellasdcoffsetremovalfilters.
– ProgrammableIIRHigh-PassFilter to
MinimizeDCOffset Low power consumption and integration of multiple
channels in a small package makes the device
– ProgrammableDigitalGain:0dBto12dB
attractive for high channel count data acquisition
• Low-FrequencyNoiseSuppressionMode systems. The device is available in a compact 9-mm
• ProgrammableMappingBetweenADCInput × 9-mm QFN-64 package. The ADS5296A is
specified over the –40°C to +85°C operating
ChannelsandLVDS OutputPins
temperaturerange.
• ChannelAveragingMode
• VarietyofLVDSTestPatternstoVerify
DataCapturebyFPGAor Receiver
• Package:9-mm× 9-mmQFN-64
APPLICATIONS
• UltrasoundImaging
• CommunicationApplications
• MultichannelDataAcquisition
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof
TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
Alltrademarksarethepropertyoftheirrespectiveowners.
2
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2013,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
ADS5296A
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore
susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
ORDERING INFORMATION(1)
PRODUCT PACKAGE-LEAD PACKAGEDESIGNATOR SPECIFIEDTEMPERATURERANGE
ADS5296A QFN-64 RGC –40°Cto+85°C
(1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orvisitthe
deviceproductfolderatwww.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Overoperatingfree-airtemperaturerange,unlessotherwisenoted.
PARAMETER VALUE UNIT
AVDD –0.3to2.2 V
Supplyvoltagerange
LVDD –0.3to2.2 V
AGNDandLGND –0.3to0.3 V
Voltagebetween: AVDDtoLVDD(whenAVDDleadsLVDD) 0to2.2 V
LVDDtoAVDD(whenLVDDleadsAVDD) 0to2.2 V
IN_p,IN_n –0.3tomin(2.2,AVDD+0.3) V
RESET,SCLK,SDATA,CS,PD,SYNC –0.3to3.6 V
Voltageappliedto:
CLKP,CLKN(2) –0.3tomin(2.2,AVDD+0.3) V
Digitaloutputs –0.3tomin(2.2,LVDD+0.3) V
Operatingfree-air,T –40to+85 °C
A
Temperaturerange Operatingjunction,T +105 °C
J
Storage,T –55to+150 °C
stg
Electrostaticdischarge(ESD)rating Humanbodymodel(HBM) 2000 V
(1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings
only,anddonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended
OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
(2) WhenAVDDisturnedoff,TIrecommendsswitchingofftheinputclock(orensuringthevoltageonCLKPandCLKNislessthan|0.3V|.
ThissettingpreventstheESDprotectiondiodesattheclockinputpinsfromturningon.
THERMAL INFORMATION
ADS5296
THERMALMETRIC(1) QFN(RGC) UNITS
64PINS
θ Junction-to-ambientthermalresistance 22.8
JA
θ Junction-to-case(top)thermalresistance 6.9
JCtop
θ Junction-to-boardthermalresistance 2.4
JB
°C/W
ψ Junction-to-topcharacterizationparameter 0.1
JT
ψ Junction-to-boardcharacterizationparameter 2.4
JB
θ Junction-to-case(bottom)thermalresistance 0.2
JCbot
(1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953.
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RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
SUPPLIES
AVDD Analogsupplyvoltage 1.7 1.8 1.9 V
LVDD Digitalsupplyvoltage 1.7 1.8 1.9 V
ANALOGINPUTS
VID Differentialinputvoltagerange 2 VPP
Inputcommon-modevoltage VCM±0.05 V
REFT Externalreferencemode,top 1.45 V
REFB Externalreferencemode,bottom 0.45 V
VCM Common-modevoltageoutput 0.95 V
CLOCKINPUT
4-channel,10-bitADCwithinterleaving 20 200 MSPS
4-channel,12-bitADCwithinterleaving 20 160 MSPS
Inputclockfrequency(1/tC)
8-channel,10-bitADCwithoutinterleaving 10 100 MSPS
8-channel,12-bitADCwithoutinterleaving 10 80 MSPS
Sine-wave,ac-coupled 0.2 1.5 VPP
Inputclockamplitudedifferential
(VCLKP–VCLKN) LVPECL,ac-coupled 0.2 1.6 VPP
LVDS,ac-coupled 0.2 0.7 VPP
InputclockCMOSsingle-ended VILwith<0.1-mAcurrentsink <0.3 V
(VCLKP) VIH >1.5 V
Inputclockdutycycle 35 50 65 %
DIGITALOUTPUTS
1x
ADCLKPandADCLKNoutputs(LVDS) MHz
(samplerateinMSPS)
6xor5x
LCLKPandLCLKNoutputs(LVDS) MHz
(samplerateinMSPS)
12xserialization 960 Mbps
Outputdatarate
10xserialization 1000 Mbps
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ELECTRICAL CHARACTERISTICS: General
TypicalvaluesareatT =+25°C,AVDD=1.8V,LVDD=1.8V,50%clockdutycycle,and–1-dBFSdifferentialanaloginput,
A
unlessotherwisenoted.
MinimumandmaximumvaluesareacrossthefulltemperaturerangeofT =–40°CtoT =+85°C,AVDD=1.8V,and
MIN MAX
LVDD=1.8V.
8-CHANNEL,12-BIT 4-CHANNEL,10-BIT
(Non-Interleaving) (Interleaving)
PARAMETER TESTCONDITIONS MIN TYP MAX MIN TYP MAX UNIT
RESOLUTION
Resolution 12 10 Bits
ANALOGINPUTS
Differentialinputvoltagerange
(0-dBgain) 2.0 2.0 VPP
Differentialinputresistance Atdc >1 >1 kΩ
Differentialinputcapacitance Atdc 2.2 2.2 pF
Analoginputbandwidth >500 >500 MHz
Analoginputcommon-modecurrent
1 1 µA/MSPS
(perinputpin)
VCM Common-modeoutputvoltage 0.95 0.95 V
VCMoutputcurrentcapability 5 5 mA
DYNAMICACCURACY
EO Offseterror –20 20 –20 20 mV
Resultingfrominternal
EGREF Gainerror referenceinaccuracyalone –1.5 1.5 –1.5 1.5 %FS
EGCHAN Ofchannelitself 0.5 0.5 %FS
EGCHANtemperaturecoefficient <0.01 <0.01 Δ%FS/°C
POWERSUPPLY
80MSPS,non-interleaving 176 mA
IAVDD Analogsupplycurrent
200MSPS,interleaving 207 227 mA
80MSPSwith100-Ωexternal
111 mA
termination
ILVDD Outputbuffersupplycurrent
200MSPSwith100-Ωexternal
125 148 mA
termination
80MSPS,non-interleaving 317 mW
AVDD Analogpower
200MSPS,interleaving 372 408.6 mW
80MSPSwith100-Ωexternal
199 mW
termination
LVDD Digitalpower
200MSPSwith100-Ωexternal
225 266.4 mW
termination
80MSPSwith100-Ωexternal
516 mW
termination
Totalpower
200MSPSwith100-Ωexternal
597 675 mW
termination
Globalpower-down 40 40 mW
Standbypower 175 190 mW
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ELECTRICAL CHARACTERISTICS: Dynamic Performance
TypicalvaluesareatT =+25°C,AVDD=1.8V,LVDD=1.8V,maximumratedinputclockfrequency,50%clockdutycycle,
A
and–1-dBFSdifferentialanaloginput,unlessotherwisenoted.
MinimumandmaximumvaluesareacrossthefulltemperaturerangeofT =–40°CtoT =+85°C,AVDD=1.8V,and
MIN MAX
LVDD=1.8V.
8-CHANNEL,12-BIT 4-CHANNEL,10-BIT
(Non-Interleaving) (Interleaving)
PARAMETER TESTCONDITIONS MIN TYP MAX MIN TYP MAX UNIT
fIN=5MHz 66 70.3 59.9 61.3 dBFS
SNR Signal-to-noiseratio(1) fIN=30MHz 70.1 61 dBFS
fIN=90MHz 68.7 60.3 dBFS
fIN=5MHz 70.1 61.3 dBFS
Signal-to-noiseanddistortion
SINAD ratio fIN=30MHz 69.7 60.8 dBFS
fIN=90MHz 67.9 59.8 dBFS
ENOB Effectivenumberofbits fIN=5MHz 11.3 9.8 LSBs
fIN=5MHz 73 83 70.5 83 dBc
Spurious-freedynamic
SFDR range(1) fIN=30MHz 80 79 dBc
fIN=90MHz 76 72.5 dBc
fIN=5MHz 71 81 67.5 81 dBc
THD Totalharmonicdistortion fIN=30MHz 78 77.5 dBc
fIN=90MHz 74 70 dBc
fIN=5MHz 73 90 70.5 86 dBc
HD2 Second-harmonicdistortion fIN=30MHz 88 84 dBc
fIN=90MHz 85 83 dBc
fIN=5MHz 73 83 70.5 83 dBc
HD3 Third-harmonicdistortion fIN=30MHz 80 79 dBc
fIN=90MHz 76 72.5 dBc
Worstspur fIN=5MHz 75 93 65 79 dBc
(otherthansecondandthird fIN=30MHz 92 74 dBc
harmonics)(2)
fIN=90MHz 90 60 71 dBc
Two-toneintermodulation
IMD distortion f1=8MHz,f2=10MHz,eachtoneat–7dBFS 83 dBc
Withafull-scale,10-MHz Adjacentchannel 86 95 dBc
Crosstalk aggressorsignalappliedand
noinputonvictimchannel Farchannel 110 110 dBc
Recoveryto<1%offull-scaleaftera6-dBinput Clock
Overloadrecovery 1 1
overload cycle
PSRR ACpower-supplyrejection Fora50-mVPPsignalonAVDDsupply,upto10 >50 >50 dB
ratio MHz,nosignalappliedtoanaloginputs
DNL Differentialnonlinearity fIN=5MHz –0.8 ±0.3 +0.95 LSBs
INL Integratednonlinearity fIN=5MHz ±0.2 ±1.1 LSBs
(1) Inthe4-channelinterleavingmode,thisparameterdoesnotincludeinterleavingspur.Spurisspecifiedseparatelyaspartoftheworst
spurparameter.
(2) Inthe4-channelinterleavingmode,worstspurincludesinterleavingspur.AlsoseeFigure44,whichshowsinterleavingspuracross
inputfrequency.
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DIGITAL CHARACTERISTICS
Thedcspecificationsrefertotheconditionwherethedigitaloutputsarenotswitching,butarepermanentlyatavalidlogic
level'0'or'1'.AVDD=1.8VandDRVDD=1.8V.
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
DIGITALINPUTS(RESET,SCLK,SDATA,CS,SYNC,PDN,INTERLEAVE_MUX)
Allpinssupport1.8-Vand3.3-VCMOSlogic
VIH High-levelinputvoltage levels 1.3 V
Allpinssupport1.8-Vand3.3-VCMOSlogic
VIL Low-levelinputvoltage levels 0.4 V
IIH High-levelinputcurrent CS,SDATA,SCLK(1) VHIGH=1.8V 6 µA
IIL Low-levelinputcurrent CS,SDATA,SCLK(1) VLOW=0V 0.1 µA
DIGITALOUTPUTS(CMOSINTERFACE:SDOUT)
VOH High-leveloutputvoltage AVDD–0.1 V
VOL Low-leveloutputvoltage 0.1 V
DIGITALOUTPUTS(LVDSINTERFACE:OUT1_p,OUT1_ntoOUT8_p,OUT8_n,ADCLKp,ADCLKn,LCLKp,LCLKn)
VODH High-leveloutputdifferentialvoltage(2) 340 560 mV
VODL Low-leveloutputdifferentialvoltage(2) –560 –340 mV
VOCM Outputcommon-modevoltage 0.93 1.2 mV
(1) CS,SDATA,andSCLKhaveaninternal220-kΩpull-downresistor.
(2) Withanexternal100-Ωtermination.
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TIMING REQUIREMENTS(1)
Typicalvaluesareat+25°C,AVDD=1.8V,LVDD=1.8V,inputclockfrequency=200MSPS,sine-waveinputclock,C
LOAD
=5pF,andR =100Ω,unlessotherwisenoted.
LOAD
MinimumandmaximumvaluesareacrossthefulltemperaturerangeofT =–40°CtoT =+85°C,AVDD=1.8V,and
MIN MAX
LVDD=1.7Vto1.9V,withdecimationfiltersDISABLED.
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
tA Aperturedelay 4 ns
Aperturedelaymatching Betweenanytwochannelsofthesamedevice ±200 ps
Betweentwodevicesatthesametemperatureand
Variationofaperturedelay ±1 ns
AVDDsupply
tJ Aperturejitter Sampleuncertainty 300 fsrms
Timetovaliddataaftercomingoutofstandby 6 µs
Wake-uptime Timetovaliddataaftercomingoutofglobalpower-
100 µs
downmode
Inputclock
Interleavingdisabled 12
cycles
ADClatency(2)
Inputclock
Interleavingenabled 24
cycles
10xSERIALIZATION
tSU Datasetuptime DatavalidtoLCLKPzero-crossing 0.200 ns
tH Dataholdtime LCLKPzero-crossingtodatabecominginvalid 0.160 ns
tPDI Clockpropagationdelay Irnispinugtcelodcgkercisroinsgsoevdegrecrossovertooutputclock ×tPtDSI=+(tD4E/LA5Y) ns
tDELAY Delaytime 7.8 11.8 ns
Betweentwodevicesatthesametemperatureand
VariationoftDELAY LVDDsupply ±0.8 ns
Dutycycleofdifferentialclock
LVDSbitclockdutycycle 50 %
(LCLKP–LCLKN)
ACROSSALLSERIALIZATIONMODES
Risetimemeasuredfrom–100mVto+100mV,
tFALL Datafalltime 10MSPS≤samplingfrequency≤100MSPS 0.13 ns
Risetimemeasuredfrom–100mVto+100mV,
tRISE Datarisetime 10MSPS≤samplingfrequency≤100MSPS 0.13 ns
Risetimemeasuredfrom–100mVto+100mV,
tCLKRISE Outputclockrisetime 10MSPS≤samplingfrequency≤100MSPS 0.13 ns
Risetimemeasuredfrom–100mVto+100mV,
tCLKFALL Outputclockfalltime 10MSPS≤samplingfrequency≤100MSPS 0.13 ns
(1) Timingparametersareensuredbydesignandcharacterization,butarenottestedinproduction.
(2) Athigherfrequencies,t isgreaterthanoneclockperiod.Overalllatency=ADClatency+1.
PDI
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Table1.12xSerializationwithDecimationFiltersDisabled(1)(2)
t =(9/12)×t +
PDI S
t
DELAY
(Wheret is
DELAY
specifiedasbelow,
INPUTCLOCKFREQUENCY(MHz) SETUPTIME(ns)(3) HOLDTIME(ns)(3) ns)
NON-
INTERLEAVED INTERLEAVED OUTPUTDATA
MODE MODE(4) RATE(Mbps) MIN TYP MAX MIN TYP MAX MIN TYP MAX
10 20 120 3.80 3.80 8 13
20 40 240 1.60 1.80 8 13
40 80 480 0.80 0.69 8 13
65 130 780 0.38 0.19 8 13
80 160 960 0.22 0.14 8 13
(1) MinimumandmaximumvaluesareacrossthefulltemperaturerangeofT =–40°CtoT =+85°C,AVDD=1.8V,andLVDD=
MIN MAX
1.7Vto1.9V.
(2) Alltimingspecificationsaretakenwithdefaultoutputclockanddatadelaysettings(0ps).RefertotheProgrammableLVDSOutput
ClockandDataEdgessectionintheApplicationInformationforadditionaloutputclockanddatadelayoptions.
(3) Whendecimationfiltersareenabled,theminimumsetupandminimumholdtimefurtherreduceby100pscomparedtotheirvalueswith
thefiltersdisabled(atthesameoutputdatarate).
Example:Atan80-MHzinputclockfrequency,withdecimationby2enabled,outputdatarate=480Mbps.At480Mbps,asperTable1,
thesetuptimewiththedecimationdisabledis0.80ns.Therefore,theset-uptimewithfilterenabledis100pslower(0.8–0.1=0.7).
Similarly,theholdtimewithfilterenabledis0.59ns.
(4) RefertotheInterleavingModesectionintheApplicationInformationfordetailsoninterleavingmode.
Table2.10xSerializationwithDecimationFiltersDisabled(1)(2)
t =(8/10)×t +t
PDI S DELAY
(Wheret isspecifiedas
DELAY
INPUTCLOCKFREQUENCY(MHz) SETUPTIME(ns)(3) HOLDTIME(ns)(3) below,ns)
NON- OUTPUT
INTERLEAVED INTERLEAVED DATARATE
MODE MODE(4) (Mbps) MIN TYP MAX MIN TYP MAX MIN TYP MAX
40 80 400 0.85 1 7.8 11.8
65 130 650 0.52 0.35 7.8 11.8
80 160 800 0.33 0.19 7.8 11.8
100 200 1000 0.2 0.16 7.8 11.8
(1) MinimumandmaximumvaluesareacrossthefulltemperaturerangeofT =–40°CtoT =+85°C,AVDD=1.8V,andLVDD=
MIN MAX
1.7Vto1.9V.
(2) Alltimingspecificationsaretakenwithdefaultoutputclockanddatadelaysettings(0ps).RefertotheProgrammableLVDSOutput
ClockandDataEdgessectionintheApplicationInformationforadditionaloutputclockanddatadelayoptions.
(3) Whendecimationfiltersareenabled,theminimumsetupandminimumholdtimefurtherreduceby100pscomparedtotheirvalueswith
thefiltersdisabled(atthesameoutputdatarate).
Example:Atan80-MHzinputclockfrequency,withdecimationby2enabled,outputdatarate=400Mbps.At400Mbps,asperTable2,
thesetuptimewiththedecimationdisabledis0.85ns.Therefore,theset-uptimewithfilterenabledis100pslower(0.85–0.10=0.75).
Similarly,theholdtimewithfilterenabledis0.90ns.
(4) RefertotheInterleavingModesectionintheApplicationInformationfordetailsoninterleavingmode.
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Table3.14xSerializationwithDecimationbytwofilterenabled(DataRate=0.5x)(1)(2)(3)
OUTPUT SETUPTIME(ns) HOLDTIME(ns)
DATA
SAMPLINGFREQUENCY RATE MAX MIN TYP MAX
(MSPS) (Mbps) MIN TYP
65 455 0.73 0.75
80 560 0.54 0.50
100 700 0.32 0.25
(1) MinimumandmaximumvaluesareacrossthefulltemperaturerangeofT =–40°CtoT =+85°C,AVDD=1.8V,andLVDD=
MIN MAX
1.7Vto1.9V.
(2) Alltimingspecificationsaretakenwithdefaultoutputclockanddatadelaysettings(0ps).
(3) RefertotheProgrammableLVDSOutputClockandDataEdgessectionintheApplicationInformationforadditionaloutputclockand
datadelayoptions.
Table4.14xSerializationwithDecimationbyfour filterenabled(DataRate=0.25x)(1)(2)(3)
OUTPUT SETUPTIME(ns) HOLDTIME(ns)
DATA
SAMPLINGFREQUENCY RATE MAX MIN TYP MAX
(MSPS) (Mbps) MIN TYP
65 227.5 1.7 1.9
80 280 1.3 1.45
100 350 0.9 1.1
(1) MinimumandmaximumvaluesareacrossthefulltemperaturerangeofT =–40°CtoT =+85°C,AVDD=1.8V,andLVDD=
MIN MAX
1.7Vto1.9V.
(2) Alltimingspecificationsaretakenwithdefaultoutputclockanddatadelaysettings(0ps).
(3) RefertotheProgrammableLVDSOutputClockandDataEdgessectionintheApplicationInformationforadditionaloutputclockand
datadelayoptions.
Table5.14xSerializationwithDecimationbyeightfilterenabled(DataRate=0.125x) (1)(2)(3)
OUTPUT SETUPTIME(ns) HOLDTIME(ns)
DATA
SAMPLINGFREQUENCY RATE MAX MIN TYP MAX
(MSPS) (Mbps) MIN TYP
65 113.75 3.8 3.8
80 140 3 3
100 175 2.2 2.2
(1) MinimumandmaximumvaluesareacrossthefulltemperaturerangeofT =–40°CtoT =+85°C,AVDD=1.8V,andLVDD=
MIN MAX
1.7Vto1.9V.
(2) Alltimingspecificationsaretakenwithdefaultoutputclockanddatadelaysettings(0ps).
(3) RefertotheProgrammableLVDSOutputClockandDataEdgessectionintheApplicationInformationforadditionaloutputclockand
datadelayoptions.
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PARAMETRIC MEASUREMENT INFORMATION
Figure1 showsatimingdiagramoftheLVDSoutput voltagelevels.
OUTP
Logic 0 Logic 1
VODL=-350 mV(1) VODH= +350 mV(1)
OUTN
V
OCM
GND
(1) Withanexternal100-Ωtermination.
Figure1. LVDSOutput VoltageLevels
Figure2 showsthelatencytimingdiagram.
Sample Sample
N + 11 N + 12 Sample
Sample N + 13
N
Input Signal
tA
Input Clock CLKN
Frequency = fS CLKP
Latency = 12 Clocks tPDI
Bit Clock LCLKP
Frequency = 6x fS LCLKN
OUTP
ROautetp =u t1 D2xa tfaS OUTN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8
Sample N-1 Sample N
ADCLKN
Frame Clock
Frequency = 1x fS ADCLKP
Figure2. LatencyTimingDiagram
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