Switching Theory: Architectures and Performance in Broadband ATM Networks

424 Pages·1998·6.736 MB·English

by  Achille Pattavina

book_title Page i Tuesday, November 18, 1997 4:58 pm

Switching Theory: Architecture and Performance in Broadband ATM Networks
Achille Pattavina
Copyright © 1998 John Wiley & Sons Ltd
ISBNs: 0-471-96338-0 (Hardback); 0-470-84191-5 (Electronic)
Switching Theory
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book_title Page iii Tuesday, November 18, 1997 4:58 pm
Switching Theory
Architectures and Performance
in Broadband ATM Networks
Achille Pattavina
Politecnico di Milano, Italy
JOHN WILEY & SONS
Chichester • New York • Weinheim • Brisbane • Singapore • Toronto
book_title Page iv Tuesday, November 18, 1997 4:58 pm
Copyright  1998 by John Wiley & Sons Ltd,
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book_acks Page 5 Tuesday, November 18, 1997 4:58 pm

Switching Theory: Architecture and Performance in Broadband ATM Networks
Achille Pattavina
Copyright © 1998 John Wiley & Sons Ltd
ISBNs: 0-471-96338-0 (Hardback); 0-470-84191-5 (Electronic)
“Behold, I will send my angel who shall
go before thee, keep thee in the journey
and bring thee into the place that I have
prepared.”
(The Holy Bible, Exodus 23, 20)
toChiara
Matteo, Luca, Sara, Maria
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book_acks Page 7 Tuesday, November 18, 1997 4:58 pm
“.............
d’i nostri sensi ch’è del rimanente
non vogliate negar l’esperienza,
di retro al sol, del mondo senza gente.
Considerate la vostra semenza:
fatti non foste a viver come bruti,
ma per seguir virtute e conoscenza.”
(Dante, Inferno, Canto XXVI)
“.............
of your senses that remains, experience
of the unpeopled world behind the Sun.
Consider your origin: ye were not
formed to live like brutes, but to follow
virtue and knowledge.”
(Dante, Inferno, Canto XXVI)
book_all_TOC Page ix Tuesday, November 18, 1997 4:24 pm

Switching Theory: Architecture and Performance in Broadband ATM Networks
Achille Pattavina
Copyright © 1998 John Wiley & Sons Ltd
ISBNs: 0-471-96338-0 (Hardback); 0-470-84191-5 (Electronic)
Contents
Preface............................................................................................ xv
Chapter 1 Broadband Integrated Services Digital Network ............... 1
1.1. Current Networking Scenario..................................................... 1
1.1.1. Communication services................................................. 1
1.1.2. Networking issues........................................................ 4
1.2. The Path to Broadband Networking............................................. 6
1.2.1. Network evolution through ISDN to B-ISDN.................... 6
1.2.2. The protocol reference model........................................... 10
1.3. Transfer Mode and Control of the B-ISDN................................... 14
1.3.1. Asynchronous time division multiplexing........................... 14
1.3.2. Congestion control issues............................................... 16
1.4. Synchronous Digital Transmission............................................... 18
1.4.1. SDH basic features..................................................... 19
1.4.2. SDH multiplexing structure........................................... 21
1.4.3. Synchronization by pointers........................................... 27
1.4.4. Mapping of SDH elements............................................ 31
1.5. The ATM Standard................................................................ 33
1.5.1. Protocol reference model................................................ 34
1.5.2. The physical layer....................................................... 39
1.5.3. The ATM layer......................................................... 42
1.5.4. The ATM adaptation layer............................................ 45
1.5.4.1. AAL Type 1.............................................. 47
1.5.4.2. AAL Type 2.............................................. 48
1.5.4.3. AAL Type 3/4........................................... 48
1.5.4.4. AAL Type 5.............................................. 49
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x Contents
1.5.4.5. AAL payload capacity................................... 50
1.6. References............................................................................ 51
1.7. Problems............................................................................. 52
Chapter 2 Interconnection Networks............................................. 53
2.1. Basic Network Concepts.......................................................... 53
2.1.1. Equivalence between networks........................................ 57
2.1.2. Crossbar network based on splitters and combiners................ 60
2.2. Full-connection Multistage Networks........................................... 63
2.3. Partial-connection Multistage Networks........................................ 64
2.3.1. Banyan networks....................................................... 65
2.3.1.1. Banyan network topologies.............................. 66
2.3.1.2. Banyan network properties.............................. 70
2.3.2. Sorting networks........................................................ 75
2.3.2.1. Merging networks......................................... 76
2.3.2.2. Sorting networks........................................... 80
2.4. Proof of Merging Schemes......................................................... 86
2.4.1. Odd–even merge sorting............................................... 86
2.4.2. Bitonic merge sorting................................................... 87
2.5. References............................................................................ 89
2.6. Problems............................................................................. 90
Chapter 3 Rearrangeable Networks............................................... 91
3.1. Full-connection Multistage Networks........................................... 91
3.2. Partial-connection Multistage Networks........................................ 96
3.2.1. Partially self-routing PC networks................................... 96
3.2.1.1. Horizontal extension..................................... 97
3.2.1.2. Vertical replication...................................... 103
3.2.1.3. Vertical replication with horizontal extension...... 107
3.2.1.4. Bounds on PC rearrangeable networks.............. 109
3.2.2. Fully self-routing PC networks..................................... 114
3.2.3. Fully self-routing PC networks with output multiplexing..... 118
3.3. Bounds on the Network Cost Function...................................... 123
3.4. References.......................................................................... 124
3.5. Problems........................................................................... 126
Chapter 4 Non-blocking Networks ............................................. 127
4.1. Full-connection Multistage Networks......................................... 127
4.1.1. Two-stage network.................................................... 127
4.1.2. Three-stage network.................................................. 128
4.1.3. Recursive network construction...................................... 130
4.2. Partial-connection Multistage Networks...................................... 134
4.2.1. Vertical replication.................................................... 134
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Contents xi
4.2.2. Vertical replication with horizontal extension..................... 136
4.2.3. Link dilation........................................................... 142
4.2.4. EGS networks......................................................... 144
4.3. Comparison of Non-blocking Networks...................................... 150
4.4. Bounds on the Network Cost Function....................................... 152
4.5. References.......................................................................... 154
4.6. Problems............................................................................ 155
Chapter 5 The ATM Switch Model.............................................. 157
5.1. The Switch Model................................................................ 159
5.2. ATM Switch Taxonomy......................................................... 163
5.3. References.......................................................................... 165
Chapter 6 ATM Switching with Minimum-Depth
Blocking Networks..................................................... 167
6.1. Unbuffered Networks............................................................ 168
6.1.1. Crossbar and basic banyan networks............................... 168
6.1.1.1. Basic structures........................................... 168
6.1.1.2. Performance............................................... 169
6.1.2. Enhanced banyan networks.......................................... 172
6.1.2.1. Structures................................................. 172
6.1.2.2. Performance............................................... 175
6.2. Networks with a Single Plane and Internal Queueing..................... 177
6.2.1. Input queueing........................................................ 181
6.2.2. Output queueing...................................................... 184
6.2.3. Shared queueing....................................................... 192
6.2.4. Performance............................................................ 197
6.3. Networks with Unbuffered Parallel Switching Planes....................... 204
6.3.1. Basic architectures..................................................... 204
6.3.2. Architectures with output queueing................................. 205
6.3.2.1. Specific architectures..................................... 206
6.3.2.2. Performance............................................... 209
6.3.3. Architectures with combined input–output queueing............. 212
6.3.3.1. Models for performance analysis....................... 213
6.3.3.2. Performance results...................................... 216
6.4. Additional Remarks.............................................................. 221
6.5. References.......................................................................... 222
6.6. Problems............................................................................ 224
Chapter 7 ATM Switching with Non-Blocking Single-Queueing
Networks ...................................................................227
7.1. Input Queueing................................................................... 229
7.1.1. Basic architectures..................................................... 229
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xii Contents
7.1.1.1. The Three-Phase switch............................... 229
7.1.1.2. The Ring-Reservation switch......................... 234
7.1.2. Performance analysis................................................. 236
7.1.2.1. Asymptotic throughput................................. 237
7.1.2.2. Packet delay.............................................. 239
7.1.2.3. Packet loss probability.................................. 240
7.1.3. Enhanced architectures............................................... 241
7.1.3.1. Architecture with channel grouping................... 242
7.1.3.2. Architecture with windowing.......................... 251
7.2. Output Queueing................................................................ 259
7.2.1. Basic architectures..................................................... 259
7.2.2. Performance analysis................................................. 263
7.3. Shared Queueing................................................................. 267
7.3.1. Basic architectures..................................................... 267
7.3.2. Performance analysis................................................. 271
7.4. Performance Comparison of Different Queueings........................... 274
7.5. Additional Remarks............................................................. 276
7.6. References.......................................................................... 277
7.7. Problems........................................................................... 279
Chapter 8 ATM Switching with Non-Blocking Multiple-Queueing
Networks ...................................................................281
8.1. Combined Input–Output Queueing.......................................... 284
8.1.1. Basic architectures..................................................... 284
8.1.1.1. Internal queue loss...................................... 284
8.1.1.2. Internal backpressure.................................... 288
8.1.2. Performance analysis................................................. 295
8.1.2.1. Constrained output queue capacity................... 296
8.1.2.2. Arbitrary input and output queue capacities........ 299
8.1.3. Architectures with parallel switching planes....................... 315
8.2. Combined Shared-Output Queueing......................................... 317
8.2.1. Basic architecture...................................................... 318
8.2.2. Performance analysis................................................. 320
8.3. Combined Input-Shared Queueing........................................... 324
8.3.1. Basic architectures.................................................... 325
8.3.2. Performance analysis................................................. 327
8.4. Comparison of Switch Capacities in Non-blocking Switches............. 331
8.5. Additional Remarks............................................................. 333
8.6. References.......................................................................... 334
8.7. Problems........................................................................... 335