Self-Healing Design Methodologies for Analog Integrated Circuits

102 Pages·2012·2.96 MB·English

by  Soner Yaldiz

SELF-HEALING DESIGN
METHODOLOGIES FOR ANALOG
INTEGRATED CIRCUITS
Submitted in partial fulfillment of the requirements for
the degree of
Doctor of Philosophy
in
Electrical and Computer Engineering
Soner Yaldiz
B.S., Microelectronics, Sabanci University
M.S., Electrical and Computer Engineering, Koc University
Carnegie Mellon University
Pittsburgh, PA
January, 2012
Acknowledgments
I would like to express my gratitude to my advisor, Professor Larry Pileggi, whose vision,
expertise and optimism I admire. I would like to thank my dissertation committee members,
Professor Andrzej Strojwas (CMU), Professor Xin Li (CMU), Dr. Arun Natarajan (IBM)
and Dr. Vyacheslav (Slava) Rovner (PDF Solutions) for their guidance, help and feedback
during this work.
I would also like to express my gratitude to my love, Lale Muazzez Yaldiz, my parents,
Nadide and Nevzat Yaldiz, my brother Taner Yaldiz and his family, and all members of
Aricioglu family for their love and support.
IwouldliketothankGokceKeskinforhisclosefriendship,support,helptosolvetechnical
issues and for motivating me whenever I get frustrated. I also would like to thank Pinar
Donmez, Volkan Ediz, Oznur Tastan, Tankut Dogrul, Umut Arslan, Emre Karagozler, Cagla
Cakir and Ekin Sumbul for their invaluable support and friendship.
I would like to thank Bodhisatwa Sadhu, Mark Ferriss, Jean-Olivier Plouchart, Scott
Reynolds, Jose Tierno and Daniel Friedman for their support, guidance and contributions
to this research during my internship at IBM. I also would like to thank Jian Wang, Jon
Proesel, Brian Taylor, Bin Wan, Yu-Tsun Chien, Vehbi Calayir, Fa Wang and numerous
other fellow students for their support, help and contributions.
This research has been supported by the Center for Circuit and System Solutions Fo-
cus Center, one of six research centers funded under the Focus Center Research Program,
a Semiconductor Research Corporation entity and sponsored by the Defense Advanced Re-
search Projects Agency Self-Healing Mixed-Signal Integrated Circuits program under Air
Force Research Laboratory contract FA8650-09-C-7924. The views expressed are those of
the author and do not reflect the official policy or position of the Department of Defense or
the United States Government.
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Abstract
Increasing process variability and shrinking voltage headroom in advanced silicon processes
havelimitedtheefficacyofexistingdesignandlayouttechniques,especiallyforanalogcircuits
that push the performance envelope. Process variations and high-performance specifications
has started to cause unpredictable and unacceptable product yield that requires new de-
sign methodologies with post-manufacturing tuning capability. Self-healing design style, in
which a tunable analog circuit is integrated together with performance sensors and a tuning
algorithm, can restore the performance loss due to process and environment variability. Fur-
thermore, self-healing can be utilized to optimize the circuits with multiple operating modes
where the performance is sensitive to the circuit state.
In this dissertation, we address what we consider to be the major challenges in designing
self-healing systems with digital tuning: integrated performance sensing; robust algorithm
design and verification before manufacturing. We present a general review of self-healing
design challenges, important design trade-offs and propose general guidelines. We propose
the use of indirect sensing for performance metrics that are either difficult or impractical to
measure using integrated circuits. We then present a catalog of techniques for self-healing
system verification including circuit simulation, behavioral modeling and simulation. We
also explore applicability of formal techniques towards verification of self-healing systems.
To demonstrate our work we focus specifically on self-healing challenges as they relate to
the design of phase locked loops (PLL) - a challenging design example that requires multiple
self-healing loops for higher performance. We apply indirect sensing method for phase noise
in voltage controlled oscillators and frequency response of PLL’s. We also present a hybrid
PLL model that enables reachability analysis and discuss the generalization of reachability
analysis to self-healing circuits.
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Contents
1 Introduction 1
1.1 Actuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.5 Contributions and Organization . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Background 10
2.1 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Past Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Indirect Performance Sensing 18
3.1 Indirect Sensor Design Methodology . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 Indirect Phase Noise Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1 Differential Colpitts Oscillator . . . . . . . . . . . . . . . . . . . . . . 24
3.2.2 Linearized Transconductance Oscillator . . . . . . . . . . . . . . . . . 34
3.3 Indirect Frequency Response Sensing . . . . . . . . . . . . . . . . . . . . . . 41
3.3.1 Dual-Path Charge-Pump PLL . . . . . . . . . . . . . . . . . . . . . . 43
3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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4 Verification of Self-Healing Systems 50
4.1 Overview of Analog Verification . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2 Actuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.3 Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.4 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5 Towards Formal Verification of Self-Healing Systems 69
5.1 Overview of Formal Analog Verification . . . . . . . . . . . . . . . . . . . . . 69
5.2 Reachability Analysis for PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.3 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6 Conclusion 79
Appendices 88
.1 Behavioral Model of Phase Frequency Detector and Charge Pump in Verilog-
AMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
.2 Behavioral Model of Voltage Controlled Oscillator and Frequency Divider in
Verilog-AMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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List of Tables
3.1 Indirect phase noise sensor accuracy . . . . . . . . . . . . . . . . . . . . . . . 38
3.2 VCO Tank Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3 PLL parameters and metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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List of Figures
1.1 Self-healing system with digital tuning. . . . . . . . . . . . . . . . . . . . . . 3
1.2 Insufficient tuning range and resolution. . . . . . . . . . . . . . . . . . . . . 4
1.3 Iterative heuristic search for non-convex and convex actuation. . . . . . . . . 7
2.1 Charge-pump phase locked loop. . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Dual-path charge-pump phase locked loop. . . . . . . . . . . . . . . . . . . . 12
2.3 Phase locking in charge-pump phase locked loop. . . . . . . . . . . . . . . . 13
2.4 Power spectrum of VCO signal with and without phase noise. . . . . . . . . 13
2.5 LC tank with digitally switched capacitor array. . . . . . . . . . . . . . . . . 15
2.6 Digital automatic amplitude control loop. . . . . . . . . . . . . . . . . . . . . 16
2.7 On-chip phase noise sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.8 On-chip period jitter sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Self-healing using indirect performance sensor. . . . . . . . . . . . . . . . . . 22
3.2 Differential Colpitts voltage controlled oscillator. . . . . . . . . . . . . . . . . 25
3.3 Tuning of differential Colpitts VCO under nominal conditions. . . . . . . . . 26
3.4 Variation in phase noise of differential Colpitts VCO due to coarse frequency
bands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5 Variation in phase noise of differential Colpitts VCO due to temperature. . . 27
3.6 Variation in phase noise of differential Colpitts VCO due to process. . . . . . 28
3.7 RMS error in estimated phase noise versus polynomial order. . . . . . . . . . 29
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3.8 RMS error in estimated phase noise versus number of non-zero coefficients in
quadratic model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.9 Simulated phase noise versus phase noise estimated by indirect sensor. . . . . 30
3.10 Self-healing algorithm for VCO phase noise. . . . . . . . . . . . . . . . . . . 31
3.11 Simulated parametric yield of phase noise achieved by ideal, non-healing and
self-healing design for varying target. . . . . . . . . . . . . . . . . . . . . . . 32
3.12 Normalized simulated average power dissipation of ideal, non-healing and self-
healing design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.13 Linearized transconductance VCO. . . . . . . . . . . . . . . . . . . . . . . . 35
3.14 Tuning of linearized transconductance VCO under nominal conditions. . . . 36
3.15 Variation in phase noise of linearized transconductance VCO due to coarse
frequency bands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.16 Variation in phase noise of linearized transconductance VCO due to process. 37
3.17 RMS error in estimated phase noise versus polynomial order. . . . . . . . . . 39
3.18 RMS error in estimated phase noise versus number of non-zero coefficients in
quadratic model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.19 Measured parametric yield of phase noise achieved by ideal, non-healing and
self-healing design for varying target. . . . . . . . . . . . . . . . . . . . . . . 40
3.20 Normalized measured average power dissipation of ideal, non-healing and self-
healing design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.21 Phase error injection by temporary change in division ratio. . . . . . . . . . 42
3.22 Crossover and overshoot measurement in prior work. . . . . . . . . . . . . . 42
3.23 Single and proposed repetitive phase error injection. . . . . . . . . . . . . . . 43
3.24 VCO frequency versus integral path voltage. . . . . . . . . . . . . . . . . . . 45
3.25 VCO frequency gain versus input voltage. . . . . . . . . . . . . . . . . . . . 45
3.26 Gain peaking versus bandwidth in the simulated data. . . . . . . . . . . . . 46
3.27 Bandwidth versus first crossover. . . . . . . . . . . . . . . . . . . . . . . . . 47
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3.28 Gain peaking versus first crossover. . . . . . . . . . . . . . . . . . . . . . . . 47
3.29 Accuracy of indirect bandwidth sensor for varying number of repetitions. . . 48
3.30 Accuracy of indirect gain peaking sensor for varying number of repetitions. . 48
4.1 Divide-by-2 prescaler with tunable resistive loads and bias voltage. . . . . . . 54
4.2 Charge pump up and down currents as a function of output voltage. . . . . . 56
4.3 Comparison of hyperbolic tangent approximation of the varactor with circuit
simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.4 Frequency tuning and gain curves for at band 13. . . . . . . . . . . . . . . . 58
4.5 Transient simulation of different PLL models. . . . . . . . . . . . . . . . . . 60
4.6 Transient simulation of the nonlinear PLL model at two different frequencies. 61
4.7 Crossover measurement in the presence of static offset. . . . . . . . . . . . . 61
4.8 Self-healing system with actuation and sensing delay. . . . . . . . . . . . . . 62
4.9 Frequency band selection algorithm. . . . . . . . . . . . . . . . . . . . . . . . 63
4.10 Transient simulation of frequency selection algorithm for N = 16. . . . . 64
WAIT
4.11 Transient simulation of frequency selection algorithm for N = 32. . . . . 64
WAIT
4.12 Transient simulation of frequency selection algorithm for N = 64. . . . . 65
WAIT
4.13 Transient simulation of frequency selection algorithm for N = 128. . . . 65
WAIT
4.14 Analog system with multiple self-healing loops. . . . . . . . . . . . . . . . . 66
4.15 Unstable system due to interdependent self-healing loops. . . . . . . . . . . . 67
4.16 PLL with multiple self-healing loops. . . . . . . . . . . . . . . . . . . . . . . 68
5.1 Fourth order dual-path charge-pump phase locked loop. . . . . . . . . . . . . 73
5.2 Hybrid automaton for phase frequency detector. . . . . . . . . . . . . . . . . 76
5.3 Reachable sets of the first 200 cycles. . . . . . . . . . . . . . . . . . . . . . . 78
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Chapter 1
Introduction
Historically, analog integrated circuits employed numerous design and layout techniques
to reduce sensitivity to systematic process, random process and environment variability.
Examples include bandgap references to reduce sensitivity to supply and temperature vari-
ations, common-mode feedback and self-biasing to reduce sensitivity to process variations,
relative device sizing and careful layout techniques to minimize random mismatch [1, 2, 3, 4].
A common practice is to design the circuit to achieve higher performance than the specifica-
tions with large margins (also known as overdesign). However, increasing process variability
and shrinking voltage headroom in advanced silicon processes have limited the efficacy of
these techniques. Random with-in die variability, such as random dopant fluctuations, can-
not be mitigated effectively by regular layout, device sizing or ratioing. Moreover, overdesign
is no longer practical in circuits that push the performance envelope to maximize capabilities
of nanoscale CMOS circuits. Thus, process variations and high-performance specifications
has started to cause unpredictable and unacceptable product yield that requires new design
methodologies with post-manufacturing (a.k.a. post-silicon) tuning capability.
The motivation behind post-manufacturing adjustment is to introduce tuning knobs to a
circuit that enables trading off different performance metrics to meet design specifications.
The area and power cost of incorporating tuning knobs to an analog circuit is justified when
1