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NASA Technical Reports Server (NTRS) 20060028446: Recent Results on SEU Hardening of SiGe HBT Logic Circuits PDF

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Preview NASA Technical Reports Server (NTRS) 20060028446: Recent Results on SEU Hardening of SiGe HBT Logic Circuits

Recent Results on SEU Hardening of SiGe HBT Logic Circ Ramkumar Krithivasan, Paul W. Marshalll, Mustayeen Nayeem, Akil K. Sutton, Wei-Min Lance Kuo, Becca M. Haugerud, Laleh Najafizadeh, John D. Cressler, Martin A. Carts*, Cheryl J. MarshalP, Guofu Niu3, Robert Reed4, Barbara A. Randalls, Charles A. Burfields, and Barry Gilberts Georgia Institute of Technology, Atlanta, GA 30332 'consultant to NRL, Washington, DC 20375 2NASA-GSFC, Greenbelt, MD 20771 3Aubum University, Auburn, AL 36849 4VanderbiltU niversity, Nashville, TN 37235 5Mayo Clinic, Rochester, MN 55901 SEE Symposium 2006: Long Beach, CA; April 9-72,2006 This work was supporfed by NASA NEPP, the DTRA Rad Hard Microelectronics Program, the DARPA RHBD Program, and the GEDC at Georgia Tech IotepimnkdbyPsul W MaohallatUleMOGS~~EvenfElsS~um[SEESYM),pipOl,l2 WGtOApnli2,2006m1QngBeach,CA Outline Introduction 0 TID and SEU in SiGe Technology RHBD Techniques 0 Circuit-Level Techniques Device-Level Techniques 9 Experiment 0 Heavy-Ion Data and Analysis 0 To be presented by Paul W. Marshall at the 2006 Single Event Effects Symposium (SEESYM), April IO, 2006 to April 12,2006 in Long Beach, CA. 1 SiGe HBT technology is robust to TID radiation, as built 0 However, TID tolerance does not ensure SEU tolerance 0 Develop RHBD techniques for SiGe technology 0 - identify candidate device and circuit-level RHBD approaches * Implement digital building blocks in IBM SiGe 8HP Experimentally evaluate effectiveness of RHBD approaches 0 “Total Dose and SEU Tolerant SiGe HBT Devices I Circuits” SiGe Technolo - 3rd-Generation SiGe HBT Technology (200 GHz) IBM 8HP - 0.12 um emitter width - raised extrinsic base n’hfta Doptd Emitter - reduced thermal cycle - in-situ polysilicon emitter - deep trench isolation slle~r - shallow trench isolation - no radiation hardening! shilllow Trench n’ WcdM To be presented by Paul W. Marshall at the 2006 Single Event Effects Symposium (SEESYM), April IO, 2006 to April 12,2006 in Long Beach, CA. 2 Proton Response Very Minimal Proton Damage in 8HP Benefit of Epi-base Structure + High Doping Levels Thus far, VERY encouraging results for TID in SiGe p 10-1 5 z : - 1~ d E l@ i! 0 0.2 0.4 0.6 0.8 1.0 1.2 0 0.2 0.4 0.6 0.8 1.0 1.2 Bas-EmiHer Voltage (VJ Base-Emitter Voltage (V) 63 MeV protons Tobeptesentedby Par1 W Marshall at 2W6 SingleEvent E&% Swum(S EESYM). npnl IO. 2W6 toppll12.2W6 1nI.w Beach. CA 5HP SEU Data Observed SEU Sensitivity in SiGe HBT Shift Registers 0 - low LET threshold + high saturated cross-section (bad news!) Ill-V Circuit-level Hardening Schemes Not Effective (CSH) 0 1 .OE-03 1 .OE-04 I. OE45 1. OE-06 1. OE-07 1 .OE-08 P. Marshall et al., IEEE WS,4 1, p. 2669, 2000. 1 .OE-09 0.0 10.0 20.0 30.0 40.0 55.0 60.0 70.0 80 1 .o LET (MeV x cm I mg) To be presented by Paul W. Marshall at the 2006 Single Event Effects Symposium (SEESYM), April 10,2006 to April 12,2006 in Long Beach, CA. 3 Circuit-Level RHBD 16-bit CML shift registers with identical clock-tree arch. 0 SRs implemented with three types of D-flip flops (DFFs) -unhardened CML master-slave (MS) DFF (std. SR,baseline) -dual-interleaved MS DFF (DI SR) -gated-feedback cell (GFC) MS DFF (GFC SR) 16-bit SR Std. MS DFF DATA Ground Gmuad oteptesentedby PdW Marshall at1Ule2006Smgle Event En& Symoslum (SEESYM),n pnl IO. Mcs !~~Apli12.200in6 Lwg Beach. CA I Circuit-Level RHBD DI DFF: limited transistor-level decoupling in storage cell .G FC DFF: OR-gate logic correction and load diode clamps DI SR and GFC SR featured rtai, = I mA & std. SR Itair= 0.5 mA Dl DFF Master Stage of GFC DFF To be presented by Paul W. Marshall at the 2006 Single Event Effects Symposium (SEESYM), April IO, 2006 to April 12,2006 in Long Beach, CA. 4 I j\ Register-Level RHBD I u DI TMR: triple module redundancy in DI SR GFC TMR: triple module redundancy in GFC SR DI TMR and GFC TMR featured ltai=, 0.5 mA 0 Voting performed using parallel GFClunhardened voters Reduced deep-trench area a improved cross-section Trench area in CBE (RHBD) device reduced by 73% Baseline circuit features CBEBC devices A, = 0.12~0.52y m2 (CBE) RHBD device To be presented by Paul W. Marshall at the 2006 Single Event Effects Symposium (SEESYM), April IO, 2006 to April 12,2006 in Long Beach, CA. 5 Experiment Heavy ion test was performed at TAMU Cyclotron 0 15 MeV/amu Ne, Ar, Xe ions used at varying incidence BERT methods used in testing at data rates 250 Mbps 0 Y. L s Ram 8HP RHBD SR Test Block Diagram ToteepasendbyPaulW I 1 Cross-Section vs. LET Low pwr. DI SR with same as std. SR & 2x sensitive nodes, 0 showed 2.5~im provement in a,,, (> expected by I. 85x) Limiting aof 2.8,5.8,12 MeV-cm*/mg for DI TMR, 1. To be presented by Paul W. Marshall at the 2006 Single Event Effects Symposium (SEESYM), April 10,2006 to April 12,2006 in Long Beach, CA. 6 aincreased with data rate at all LETS except in DI TMR 0 While TMR in DI SR improved asignificantly, it offered little improvement in GFC SR and adegraded with data rate * No saturation of awas noted at higher data rates 0.4 LET 8.5 MeV-cm21mg r + 6 0.3 Dual-lnterkrsnd SR (Dl SA) k 0 Low Power DI SR 2s .- 0.2 AI GGFF CC TSRM c. 0 a, 9 0.1 E -.- nn ... 0.0 0.5 1 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0.0 0.5 1 1.5 2.0 2.5 3.0 3.5 4.0 4. Data Rate (Gbps) Data Rate (Gbps) rotepresantedbyParlW MarshaIal~2006~~e~E~~~(SEESYM),~IiO,2006~O~IiZ,2006In~W,CA I? No signature of temporal multiple bit upsets in DI TMR 0 Zero avg. error corresponds to limiting aobserved in GFC SR & TMR, and DI SR & TMR All circuits showed avg. error / event lower than std. SR -I--. 0.0 0.5 1 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0.0 0.5 1 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Data Rate (Gbps) Data Rate (Gbps) TotspessntsdbypauWi uarShallslth2006L c#eEvsnt El(edaSvmposium(SEESYM),ApllI O. WtoA plIi2,WinlangW. CA 1 To be presented by Paul W. Marshall at the 2006 Single Event Effects Symposium (SEESYM), April 10,2006 to April 12,2006 in Long Beach, CA. 7 * LET thresholds were obtained from Weibull fit and LET,,% e Lth improvement of 200x observed in DI SR and TMR over std. SR at 1 Gbps I Topology, Power conslimption, and estimated Threshold LET for the circuits. Summary RHBD techniques were developed for SiGe technology Circuit-level RHBD techniques: 0 - minimization of local transistor-level cross-coupling - triple module redundancy Device-level RHBD technique: 0 - reduction of DT enclosed sensitive volume - utilization of minimum feature-size devices * Digital building blocks were realized in IBM SiGe 8HP Digital blocks were tested for SEU response using heavy-ions Low pwr. DI SR showed 2.5~im provement in a,,, over std. SR Limiting a observed for various RHBD enhanced SRs e TMR in DI SR improved asignificantly * No temporal multiple bit upsets observed in DI TMR - Significant improvement in L,h observed in RHBD SRs YEAH! + SEU Hardening Achievable in SiGe using RHBD Techniques! TotepmmledtyP8AW ~et~xx)6Si~Evan(~~~(SEESYM),Apn~lO,zM)G&AprU12,~inLong~,CA II To be presented by Paul W. Marshall at the 2006 Single Event Effects Symposium (SEESYM), April IO, 2006 to April 12,2006 in Long Beach, CA. 8

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