Low-Power Stereo Audio DAC With Stereo Class-D Speaker Amplifier (Rev. A)

100 Pages·2014·1.4 MB·English

TLV320DAC3101
www.ti.com SLAS666A–JANUARY2010–REVISEDMAY2012
Low-Power Stereo Audio DAC With Audio Processing
and Stereo Class-D Speaker Amplifier
CheckforSamples:TLV320DAC3101
1 INTRODUCTION
PlaybackVolume-Control Settings
1.1 Features
• ProgrammablePLLforFlexibleClock
• StereoAudioDACWith95-dBSNR
Generation
123
• Supports8-kHzto192-kHzSampleRates • I2S,Left-Justified, Right-Justified, DSP,and
• Stereo 1.29-WClass-DBTL8-ΩSpeakerDriver TDM AudioInterfaces
WithDirectBatteryConnection • I2CControl WithRegisterAuto-Increment
• 25Built-InProcessingBlocks(PRB_P1–
• FullPower-DownControl
PRB_P25)ProvidingBiquadFilters,DRC, and
• PowerSupplies:
3D
– Analog: 2.7V–3.6V
• DigitalSine-WaveGeneratorfor Beepsand
– Digital Core:1.65V–1.95V
Key-Clicks(PRB_P25)
– Digital I/O: 1.1V–3.6V
• User-ProgrammableBiquadand FIRFilters
– Class-D:2.7V–5.5V(SPLVDDandSPRVDD
• TwoSingle-Ended InputsWithMixingand
≥AVDD)
Output LevelControl
• 5-mm× 5-mm 32-QFNPackage
• Stereo Headphone/LineoutandClass-D
SpeakerOutputsAvailable
• MicrophoneBias 1.2 Applications
• HeadphoneDetection • PortableAudioDevices
• DigitalMixingCapability
• MobileInternet Devices
• PinControlor RegisterControl forDigital-
• e-Books
1.3 Description
The TLV320DAC3101 is a low-power, highly integrated, high-performance DAC with selectable digital
audioprocessingblocksand24-bitstereoplayback.
Thedeviceintegratesheadphonedriversandspeakerdrivers. TheTLV320DAC3101hasasuiteof built-in
processing blocks for digital audio processing. The digital audio data format is programmable to work with
popular audio standard protocols (I2S, left/right-justified) in master, slave, DSP, and TDM modes. Bass
boost, treble, or EQ can be supported by the programmable digital signal-processing block. An on-chip
PLL provides the high-speed clock needed by the digital signal-processing block. The volume level can be
controlledbyeitherpincontrolorbyregistercontrol. Theaudiofunctionsarecontrolledusingthe I2Cserial
bus.
The TLV320DAC3101 has a programmable digital sine-wave generator and is available in a 32-pin QFN
package.
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof
TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
MATLABisatrademarkofTheMathWorks,Inc.
2
Allothertrademarksarethepropertyoftheirrespectiveowners.
3
PRODUCTIONDATAinformationiscurrentasofpublicationdate.Productsconformto Copyright©2010–2012,TexasInstrumentsIncorporated
specifications per the terms of the Texas Instruments standard warranty. Production
processingdoesnotnecessarilyincludetestingofallparameters.
TLV320DAC3101
SLAS666A–JANUARY2010–REVISEDMAY2012 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore
susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
AVSS AVDD HPVSS HPVDD SPLVSS SPRVSS SPLVDD SPRVDD
P0/R116
7-Bit
VOL/MICDET Vol
ADC
Left and Right Audio Output Stage
Volume-Control Register Power Management
P0/R117
P1/R33–R34
GPIO1 GPIO
De-Pop
SDA I2C and
SCL Soft Start
RC CLK
AIN1
AIN2
Analog Class-D Speaker
Note: Normally, Attenuation Driver
MCLK is PLLinput; 0 dB to–78 dB
however, BCLK or and Mute 6 dB to 24 dB
GPIO1 can also be P0/R63/D5–D4 (0.5-dB steps) (6-dB steps)
PLLinput.
LData Left DAC AIN1 P1/R38 P1/R42
R Data S SPLP
MCLK PLL (L+R)/2 Data DAC SPLM
Analog ClassA/B
Attenuation Headphone/Lineout
0 dB to–78 dB Driver
WCLK and Mute 0 dB to 9 dB
SDIN (0.5-dB steps) (1-dB steps)
BCLK Serial P1/R36 P1/R40
Interface Proincegss- D2i4g itdaBl Vtool AIN2 HPL
and Blocks Mute MIXER P1/R30–R31
RESET Clocks P1/R35
Analog Class-D Speaker
Attenuation Driver
0 dB to–78 dB
and Mute 6 dB to 24 dB
P0/R63/D3–D2 (0.5-dB steps) (6-dB steps)
Right DAC P1/R39 P1/R43
LData
R Data S SPRP
DAC
(L+R)/2 Data SPRM
P0/R64–R66 Analog ClassA/B
Attenuation Headphone/Lineout
0 dB to–78 dB Driver
and Mute 0 dB to 9 dB
P1/R46 2 V/2.5 V/AVDD (0.5-dB steps) (1-dB steps)
MICBIAS P1/R37 P1/R41
HPR
P1/R30–R31
IOVSS IOVDD DVSS DVDD
B0360-02
Figure1-1. Functional BlockDiagram
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NOTE
Thisdatamanualis designedusingPDFdocument-viewingfeatures thatallowquick access
to information. For example, performing a global search on "page 0 / register 27" produces
all references to this page and register in a list. This makes it easy to traverse the list and
find allinformationrelatedto apage andregister. Note thatthesearch string mustbe of the
indicated format. Also, this document includes document hyperlinks to allow the user to
quickly find a document reference. To come back to the original page, click the green left
arrownearthePDFpagenumberatthebottomofthefile.Thehot-keyforthisfunctionisalt-
left arrow on the keyboard. Another way to find information quickly is to use the PDF
bookmarks.
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2 PACKAGE AND SIGNAL DESCRIPTIONS
2.1 Package/Ordering Information
OPERATING TRANSPORTMEDIA,
PACKAGE
PRODUCT PACKAGE TEMPERATURE ORDERINGNUMBER QUANTITY
DESIGNATOR
RANGE
TLV320DAC3101IRHBT Tapeandreel,250
TLV320DAC3101 QFN-32 RHB –40°Cto85°C
TLV320DAC3101IRHBR Tapeandreel,3000
2.2 Device Information
RHB Package
(Top View)
D D S
VD M P VD VS M S D
R R L L L L S D
P P P P P P V V
S S S S S S D A
24 23 22 21 20 19 18 17
SPRVSS 25 16 AVSS
SPRP 26 15 NC
HPL 27 14 AIN2
HPVDD 28 13 AIN1
TLV320DAC3101
HPVSS 29 12 MICBIAS
HPR 30 11 VOL/MICDET
RESET 31 10 SCL
GPIO1 32 9 SDA
1 2 3 4 5 6 7 8
S D D C N K K K
VS VD VD N DI CL CL CL
O O D W B M
I I
P0048-14
Table2-1. TERMINALFUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
AIN1 13 I Analoginput#1routedtooutputmixer
AIN2 14 I Analoginput#2routedtooutputmixer
AVDD 17 – Analogpowersupply
AVSS 16 – Analogground
BCLK 7 I/O Audioserialbitclock
DIN 5 I Audioserialdatainput
DVDD 3 – Digitalpower–digitalcore
DVSS 18 – Digitalground
GPIO1 32 I/O General-purposeinput/outputandmultifunctionpin
HPL 27 O Left-channelheadphone/linedriveroutput
HPR 30 O Right-channelheadphone/linedriveroutput
HPVDD 28 – Headphone/linedriverandPLLpower
HPVSS 29 – Headphone/linedriverandPLLground
IOVDD 2 – Interfacepower
IOVSS 1 – Interfaceground
MCLK 8 I Exterrnalmasterclock
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Table2-1.TERMINALFUNCTIONS(continued)
TERMINAL
I/O DESCRIPTION
NAME NO.
MICBIAS 12 – Microphonebiasforexternalmicrophone
NC 4,15 I Noconnecton
RESET 31 I Devicereset
SCL 10 I/O I2Ccontrolbusclockinput
SDA 9 I/O I2Ccontrolbusdatainput
SPLM 19 O Left-channelclass-Dspeaker-driverinvertingoutput
SPLP 22 O Left-channelclass-Dspeaker-drivernoninvertingoutput
SPLVDD 21 – Left-channelclass-Dspeaker-driverpowersupply
SPLVSS 20 – Left-channelclass-Dspeaker-driverpowersupplyground
SPRM 23 O Right-channelclass-Dspeaker-driverinvertingoutput
SPRP 26 O Right-channelclass-Dspeaker-drivernoninvertingoutput
SPRVDD 24 – Right-channelclass-Dspeaker-driverpowersupply
SPRVSS 25 – Right-channelclass-Dspeaker-driverpower-supplyground
Volumecontrolorheadphonedetection.Notethatmicrophonedetectionisalsoavailableon
VOL/MICDET 11 I
devicesthathaveanADC.
WCLK 6 I/O Audioserialwordclock
3 ELECTRICAL SPECIFICATIONS
3.1 Absolute Maximum Ratings
overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1)
VALUE UNIT
AVDDtoAVSS –0.3to3.9 V
DVDDtoDVSS –0.3to2.5 V
HPVDDtoHPVSS –0.3to3.9 V
SPLVDDtoSPLVSS –0.3to6 V
SPRVDDtoSPRVSS –0.3to6 V
IOVDDtoIOVSS –0.3to3.9 V
Digitalinputvoltage IOVSS–0.3toIOVDD+0.3 V
Analoginputvoltage AVSS–0.3toAVDD+0.3 V
Operatingtemperaturerange –40to85 °C
Storagetemperaturerange –55to150 °C
Junctiontemperature(T Max) 105 °C
J
Powerdissipation (T Max–T )/R W
J A θJA
R thermalimpedance(withthermalpadsolderedtoboard) 35 °C/W
θJA
(1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings
only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating
Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
Table3-1.System ThermalCharacteristics(1)
PowerRatingat25°C DeratingFactor PowerRatingat70°C PowerRatingat85°C
2.3W 28.57mW/°C 1W 0.6W
(1) Thisdatawastakenusing2-oz.(0.071-mmthick)traceandcopperpadthatissolderedtoaJEDEChigh-K,standard4-layer3-in.×3-
in.(7.62-cm×7.62-cm)PCB.
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3.2 Recommended Operating Conditions
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
MIN NOM MAX UNIT
AVDD(1) ReferencedtoAVSS(2) 2.7 3.3 3.6
DVDD ReferencedtoDVSS(2) 1.65 1.8 1.95
HPVDD ReferencedtoHPVSS(2) 2.7 3.3 3.6 V
Power-supplyvoltagerange
SPLVDD(1) ReferencedtoSPLVSS(2) 2.7 5.5
SPRVDD(1) ReferencedtoSPRVSS(2) 2.7 5.5
IOVDD ReferencedtoIOVSS(2) 1.1 3.3 3.6
Resistanceappliedacrossclass-Doutputpins
Speakerimpedance 8 Ω
(BTL)
Headphoneimpedance AC-coupledtoR 16 Ω
L
Analogaudiofull-scaleinput
V AVDD=3.3V,single-ended 0.707 V
I voltage RMS
Stereolineoutputload
ACcoupledtoR 10 kΩ
impedance L
MCLK(3) Masterclockfrequency IOVDD=3.3V 50 MHz
f SCLclockfrequency 400 kHz
SCL
T Operatingfree-airtemperature –40 85 °C
A
(1) Tominimizebattery-currentleakage,theSPLVDDandSPRVDDvoltagelevelsshouldnotbebelowtheAVDDvoltagelevel.
(2) Allgroundsonboardaretiedtogether,sotheyshouldnotdifferinvoltagebymorethan0.2Vmaximumforanycombinationofground
signals.Byuseofawidetraceorgroundplane,ensurealow-impedanceconnectionbetweenHPVSSandDVSS.
(3) Themaximuminputfrequencyshouldbe50MHzforanydigitalpinusedasageneral-purposeclock.
3.3 Electrical Characteristics
At25°C,AVDD=HPVDD=IOVDD=3.3V,SPLVDD,SPRVDD=3.6V,DVDD=1.8V,f (audio)=48kHz,CODEC_CLKIN
S
=256×f ,PLL=Off,VOL/MICDETpindisabled(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
INTERNALOSCILLATOR—RC_CLK
Oscillatorfrequency 8.2 MHz
VOLUMECONTROLPIN(ADC);VOL/MICDETPINENABLED
VOL/MICDETpinconfiguredasvolumecontrol
0.5×
Inputvoltagerange (page0/register116,bitD7=1andpage0/ 0 V
AVDD
register67,bitD7=0)
Inputcapacitance 2 pF
Volumecontrolsteps 128 Steps
MICROPHONEBIAS
Page1/register46,bitsD1–D0=10 2.25 2.5 2.75
Voltageoutput V
Page1/register46,bitsD1–D0=01 2
At4-mAloadcurrent,page1/register46,bitsD1–D0
5
=10(MICBIAS=2.5V)
Voltageregulation mV
At4-mAloadcurrent,page1/register46,bitsD1–D0
7
=01(MICBIAS=2V)
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ElectricalCharacteristics(continued)
At25°C,AVDD=HPVDD=IOVDD=3.3V,SPLVDD,SPRVDD=3.6V,DVDD=1.8V,f (audio)=48kHz,CODEC_CLKIN
S
=256×f ,PLL=Off,VOL/MICDETpindisabled(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
AUDIODAC
DACHeadphoneOutput,AC-CoupledLoad=16Ω(Single-Ended),
DriverGain=0dB,ParasiticCapacitance=30pF
Full-scaleoutputvoltage(0
Outputcommon-modesetting=1.65V 0.707 Vrms
dB)
SNR Signal-to-noiseratio Measuredasidle-channelnoise,A-weighted(1) (2) 80 95 dB
THD Totalharmonicdistortion 0-dBFSinput –85 –65 dB
Totalharmonicdistortion+
THD+N 0-dBFSinput –82 –60 dB
noise
Muteattenuation 87 dB
PSRR Power-supplyrejectionratio(3) RippleonHPVDD(3.3V)=200mVp-pat1kHz –62 dB
R =32Ω,THD+N≤–60dB 20
L
P Maximumoutputpower mW
O
R =16Ω,THD+N≤–60dB 60
L
DACLineout(HPDriverinLineoutMode)
SNR Signal-to-noiseratio Measuredasidle-channelnoise,A-weighted 95 dB
THD Totalharmonicdistortion 0-dBFSinput,0-dBgain –86 dB
Totalharmonicdistortion+
THD+N 0-dBFSinput,0-dBgain –82 dB
noise
DACDigitalInterpolationFilterCharacteristics
SeeSection5.5.1.4forDACinterpolationfiltercharacteristics.
DACOutputtoClass-DSpeakerOutput;Load=8Ω(Differential),50pF
SPLVDD=SPRVDD=3.6V,BTLmeasurement,
CM=1.8V,DACinput=0dBFS, 2.2
class-Dgain=6dB,THD≤–16.5dB
Outputvoltage Vrms
SPLVDD=SPRVDD=3.6V,BTLmeasurement,
CM=1.8V,DACinput=–2dBFS, 2.1
class-Dgain=6dB,THD≤–20dB
SPLVDD=SPRVDD=3.6V,BTLmeasurement,
Output,common-mode 1.8 V
DACinput=mute,CM=1.8V,class-Dgain=6dB
SPLVDD=SPRVDD=3.6V,BTLmeasurement,
class-Dgain=6dB,measuredasidle-channelnoise,
SNR Signal-to-noiseratio 87 dB
A-weighted(withrespecttofull-scaleoutputvalueof
2.2Vrms)(1) (2)
SPLVDD=SPRVDD=3.6V,BTLmeasurement,
THD Totalharmonicdistortion –67 dB
CM=1.8V,class-Dgain=6dB
Totalharmonicdistortion+ SPLVDD=SPRVDD=3.6V,BTLmeasurement,
THD+N –66 dB
noise CM=1.8V,class-Dgain=6dB
PSRR Power-supplyrejectionratio(4) SPLVDD=SPRVDD=3.6V,BTLmeasurement, –44 dB
rippleonSPLVDD/SPRVDD=200mVp-pat1kHz
Muteattenuation 110 dB
SPLVDD=SPRVDD=3.6V,BTLmeasurement,
540
CM=1.8V,class-Dgain=18dB,THD=10%
mW
SPLVDD=SPRVDD=4.3V,BTLmeasurement,
P Maximumoutputpower 790
O CM=1.8V,class-Dgain=18dB,THD=10%
SPLVDD=SPRVDD=5.5V,BTLmeasurement,
1.29 W
CM=1.8V,class-Dgain=18dB,THD=10%
(1) Ratioofoutputlevelwith1-kHzfull-scalesine-waveinput,totheoutputlevelwiththeinputsshort-circuited,measuredA-weightedovera
20-Hzto20-kHzbandwidthusinganaudioanalyzer.
(2) Allperformancemeasurementsdonewith20-kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesuchafiltermay
resultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-passfilter
removesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues.
(3) DACtoheadphone-outPSRRmeasurementiscalculatedasPSRR=20×log(ΔV /ΔV ).
HPL HPVDD
(4) DACtospeaker-outPSRRmeasurementiscalculatedasPSRR=20×log(ΔV /ΔV ).
SPL(P+M) SPLVDD
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ElectricalCharacteristics(continued)
At25°C,AVDD=HPVDD=IOVDD=3.3V,SPLVDD,SPRVDD=3.6V,DVDD=1.8V,f (audio)=48kHz,CODEC_CLKIN
S
=256×f ,PLL=Off,VOL/MICDETpindisabled(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
DACOutputtoClass-DSpeakerOutput;Load=8Ω(Differential),50pF(Continued)
Output-stageleakagecurrent SPLVDD=SPRVDD=4.3V,deviceispowered
80 nA
fordirectbatteryconnection down(power-up-resetcondition)
DACPowerConsumption
ForDACpowerconsumptionbasedperselectedprocessingblock,seeSection5.3.
DIGITALINPUT/OUTPUT
Logicfamily CMOS
0.7×
I =5μA,IOVDD≥1.6V
V IH IOVDD V
IH
I =5μA,IOVDD<1.6V IOVDD
IH
0.3×
I =5μA,IOVDD≥1.6V –0.3
V IL IOVDD V
IL Logiclevel
I =5μA,IOVDD<1.6V 0
IL
0.8×
V I =2TTLloads V
OH OH IOVDD
0.1×
V I =2TTLloads V
OL OL IOVDD
Capacitiveload 10 pF
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3.4 Timing Characteristics
3.4.1 I2S/LJF/RJF Timing in Master Mode
Allspecificationsat25°C,DVDD=1.8V
Note:Alltimingspecificationsaremeasuredat characterizationonly.
WCLK
t (WS) t
d r
BCLK
t
f
t (DI) t (DI)
S h
DIN
T0145-10
IOVDD=1.1V IOVDD=3.3V
PARAMETER UNIT
MIN MAX MIN MAX
t (WS) WCLKdelay 45 20 ns
d
t(DI) DINsetup 8 6 ns
s
t (DI) DINhold 8 6 ns
h
t Risetime 25 10 ns
r
t Falltime 25 10 ns
f
Figure3-1.I2S/LJF/RJFTiminginMasterMode
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3.4.2 I2S/LJF/RJF Timing in Slave Mode
Allspecificationsat25°C,DVDD=1.8V
Note:Alltimingspecificationsaremeasuredat characterizationonly.
WCLK
t (WS) t
h r
t (BCLK) t (WS)
H S
BCLK
t (BCLK)
L
t (DI) t
S f
DIN
t (DI)
h
T0145-11
IOVDD=1.1V IOVDD=3.3V
PARAMETER UNIT
MIN MAX MIN MAX
t (BCLK) BCLKhighperiod 35 35 ns
H
t (BCLK) BCLKlowperiod 35 35 ns
L
t(WS) WCLKsetup 8 6 ns
s
t (WS) WCLKhold 8 6 ns
h
t(DI) DINsetup 8 6 ns
s
t (DI) DINhold 8 6 ns
h
t Risetime 4 4 ns
r
t Falltime 4 4 ns
f
Figure3-2.I2S/LJF/RJFTiminginSlaveMode
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