Low Power Digital CMOS Design

418 Pages·1995·15.317 MB·English

by  Anantha P. Chandrakasan, Robert W. Brodersen (auth.)

LOW POWER DIGITAL CMOS DESIGN
LOW POWER DIGITAL CMOS DESIGN
Anantha P. Chandrakasan
Massachusetts Institute of Technology
Robert W. Brodersen
University of California/Berkeley
"~.
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
Library or Congress Cataloging.in.Publication
A C.I.P. Catalogue record for this book is available
from the Library of Congress.
ISBN 978-1-4613-59&4-5 ISBN 978-1-4615-2325-3 (eBook)
DOI 10.1007/978-1-4615-2325-3
Copyright C 1995 by Springer Science+Business Media New York
Originally published by Kiuwer Academic Publishers in 1995
Softcover reprint of the hardcover I st edition 1995
This printing is a digital duplication of the original edition.
All rights ~served. No pan of this publication may be: reproduced, stored in a retrieval system
or tn\Jlsmittcd in any form or by any means, mechanical, pholo-copying, recording, or otherwise,
without the prior written pennission of the publisher, Springer Science+Business Media. LLC.
Printed on acidjru paptr.
PREFACE
The genesis of low power microelectronics can be traced to the invention
of the transistor in 1947. The elimination of the crushing needs for several watts
of heater power and several hundred volts of anode voltage in vacuum tubes in
exchange for transistor operation in the tens of milliwatts range was a break
through of virtually unparalleled importance in electronics. The capability to
fully utilize the low power assets of the transistor was provided by the invention
of the integrated circuit in 1958. Historically, the motivation for low power elec
tronics has stemmed from three reasonably distinct classes of need: I) the earliest
and most demanding of these is for portable battery operated equipment that is
sufficiently small in size and weight and long in operating life to satisfy the user;
2) the most recent need is for ever increasing packing density in order to further
enhance the speed of high performance systems which imposes severe restrictions
on power dissipation density; and 3) the broadest need is for conservation of
power in desk-top and desk-side systems where a competitive life cycle
cost-to-performance ratio demands low power operation to reduce power supply
and cooling costs. Viewed in toto, these three classes of need appear to encom
pass a substantial majority of current applications of electronic equipment. Low
power electronics has become the mainstream of the effort to achieve as!.
The earliest and still the most urgent demands for low power electronics
originate from the stringent requirements for small size and weight, long operat
ing life, utility and reliability of battery operated equipment such as wrist
watches, pocket calculators and cellular phones, hearing aids, implantable cardiac
pacemakers and a myriad of portable military equipments used by individual foot
soldiers. Perhaps no segment of the electronics industry has a growth potential as
explosive as that of the personal digital assistant (PDA) which has been charac
terized as a combined pocket cellular phone, pager, e-mail terminal, fax, com
puter, calendar, address directory, notebook, etc. To satisfy the needs of the PDA
for low power electronics, comprehensive approaches are proposed in this book
that include use of the lowest possible supply voltage coupled with architectural,
logic style, circuit and CMOS technology optimizations.
The antecedents of these concepts are strikingly evident in publications
from the 1960's, in which several critical principles of low power design were
formulated and codified (J. D. Meindl, Micropower Circuits, J. Wiley and Sons,
vi
1969). The first of these was simply to use the lowest possible supply voltage,
preferably a single cell battery. The second guideline was to use analog tech
niques wherever possible particularly in order to avoid the large standby power
drain of then available bipolar digital circuits. A third key principle of
micropower design that was convincingly demonstrated quite early is the advan
tage of selecting the smallest geometry, highest frequency transistors available to
implement a required circuit function, e.g. a wideband amplifier, and then scaling
down the quiescent current until the transistor gain-bandwidth product/r just sat
isfies the relevant system performance requirements. A fourth generic principle of
low power design that was clearly articulated in antiquity is the advantage of
using "extra" electronics to reduce total power drain. This trade-off of silicon
hardware for battery hardware was demonstrated e.g. for a multi-stage wideband
amplifier in which total current drain was reduced by more than an order of mag
nitude by doubling the number of stages from two to four while maintaining a
constant overall gain-bandwidth product. A final overarching principle of low
power design that was rigorously illustrated for a wide variety of circuit functions
including audio and video is that micropower design begins with ajudicious spec
ification of the required system performance and proceeds to the optimal imple
mentation that fulfills the required performance at minimum power drain.
The advent of CMOS digital technology removed quiescent power drain as
an unacceptable penalty for broadscale utilization of digital techniques in porta
ble battery operated equipment. During the 1970's a variety of new micropower
techniques were introduced and by far the most widely used product exploiting
these techniques was and is the electronic wristwatch (E. Vittoz, keynote speech
at the 1994 ISSCC). In the 1980's, the increasing level of power dissipation in
mainstream microprocessor, memory and a host of application specific integrated
circuit chips prompted an industry wide shift from NMOS and NPN bipolar tech
nologies to CMOS in order to alleviate heat removal problems. The greatly
reduced average power drain of CMOS chips provided a relatively effortless
interim solution to the problems of low power design. However, the relentless
march of microelectronics to higher packing densities and larger clock frequen
cies has, during the early 1990's, brought low power design to the forefront as a
primary requirement for mainstream microelectronics which is addressed in this
book.
James D. Meindl
Georgia Institute o/Technology
TABLE OF CONTENTS
CHAPTER 1 Introduction 1
1.1 Overview of Book . . . . . . . .4
CHAPTER 2 Hierarchy of Limits of Power 11
James D. Meindl
Joseph M. Petit Chair Professor of Microelectronics
Georgia Institute of Technology
2.1 Introduction ............ . . II
2.2 Background............. . 13
2.3 Theoretical Limits ........ . .18
2.4 Quasi-Adiabatic Microelectronics . .41
2.5 Practical Limits. . . . . . . . . . . .44
2.6 Conclusion............. .48
CHAPTER 3 Sources of Power Consumption 55
3.1 Switching Component of Power . . . 56
3.2 Short-circuit Component of Power. . 92
3.3 Leakage Component of Power. . 98
3.4 Static Power . . . . . . . . . . . . 101
3.5 Summary. ............ 102
CHAPTER 4 Voltage Scaling Approaches 105
4.1 Reliability-Driven Voltage Scaling. . . . . . . . . . 106
4.2 Technology-Driven Voltage Scaling. . . . . . . . . 108
4.3 Energy x Delay Minimum Based Voltage Scaling. . III
4.4 Voltage Scaling Through Optimal Transistor Sizing. 112
4.5 Voltage Scaling Using Threshold Reduction. .. 115
4.6 Architecture-Driven Voltage Scaling. . . . . . . . . 117
4.7 Summary....................... 139
CHAPTER 5 DC Power Supply DeSign in Portable Systems 141
Coauthored with Anthony J. Stratakos, Charles R. Sullivan, Seth R. Sanders
University of California at Berkeley
5.1 Voltage Regulation Enhances System Run-time. 142
5.2 DC-DC Converter Topology Selection .. . 146
5.3 Converter Miniaturization ........... . 157
5.4 Circuit Optimizations for High Efficiency. . . . 166
viii
CHAPTER 6 Adiabatic Switching 181
Lars Svensson
University of Southern California, Information Sciences Institute
6.1 Adiabatic Charging. . . · 184
6.2 Adiabatic Amplification · 186
6.3 Adiabatic Logic Gates . · 195
6.4 Stepwise Charging . . . · 203
6.5 Pulsed-Power Supplies. · 210
6.6 Summary . . . . . . . . · 215
6.7 Acknowledgments ... · 216
CHAPTER 7 Minimizing Switched Capacitance 219
7.1 Algorithmic Optimization . 219
7.2 Architecture Optimization. · 235
7.3 Logic Optimization .. · 245
7.4 Circuit Optimization ... . . . 249
7.5 Physical Design ...... . . . 254
7.6 Summary. . ...... . · 256
CHAPTER 8 Computer Aided Design Tools 259
8.1 Previous Work . . . . . . . . . . . . . . . . . . . . . · 260
8.2 Application of Transformations to Minimize Power .. · 266
8.3 Cost Function. . . . . . · 281
8.4 Optimization Algorithm . . . .. .. . · 297
8.5 Examples and Results . . . . . . . . . . . . . . . . . · 300
8.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . · 306
CHAPTER 9 A Portable Multimedia Terminal 309
9.1 Technology Trends for Low Power Portable Systems .. . · 312
9.2 System Partitioning for Low-power ........... . · 314
9.3 Architecture of the Portable Multimedia Terminal ...... . · 317
9.4 Low Power Implementation of the 110 Processing Modules .. · 319
9.5 System Implementation . . . . . . . . . . . . . . . . . . . . · 359
9.6 Summary. . ........................ . · 363
CHAPTER 10 Low Power Programmable Computation 367
Coauthored with Mani B. Srivastava
AT& T Bell Laboratories, Murray Hill, NJ
10.1 Architectural Approaches to Low-power. · 368
10.2 Shutdown Techniques . . . . . . . . . · 370
10.3 Architecture-Driven Voltage Reduction · 384
10.4 Summary. ......... . · 395
CHAPTER 11 Conclusions 397
INDEX 401
ACKNOWLEDGEMENTS
The majority of work described in this book began in 1991 and includes
contributions from a number of U.C. Berkeley researchers. We would particularly
like to acknowledge the contribution of Sam Sheng who was involved in develop
ing the key ideas in the early phases of our research and to Prof. Jan Rabaey and
his students who have been continually involved in all aspects of this work. We
would also like to acknowledge the invaluable feedback on our early research
efforts from Professors Teresa Meng, Charles Sodini, and Mark Horowitz. We
would like to thank Prof. Jim Meindl (Chapter 2 and preface), Tony Stratakos,
Charles Sullivan and Prof. Seth Sanders (Chapter 5), Lars Svensson (Chapter 6),
and Mani Srivastava (Chapter 10) for their contributions to this book. We would
also like to thank Arthur Abnous, Rajeevan Amirthara, David Lidsky, Thomas
Barber, Tom Miller, Tom Simon, and Carlin Vieri for reading this book and pro
viding valuable feedback.
The design tool described in Chapter 8 (HYPER-LP) was a result of a col
laborative effort with Miodrag Potkonjak and Prof. Jan Rabaey. We would also
like to thank Sean Huang for coding the local transforms used in the CAD tool,
Paul Landman for providing software to generate data with different statistics,
Renu Mehra for generating the various controllers and building the controller
model, Ingrid Verbauwhede for providing the wavelet example, Scarlett Wu for
switch-level simulation of the wavelet filter, and the rest of the HYPER team for
software support.
The design and demonstration of the InfoPad chipset and terminal
(described in Chapter 9) was a joint effort of a number of people. The first gener
ation radio and protocol group consisting of Bill Baringer, Kathy Lu, Trevor Per
ing, and Tom Truman was responsible for designing the radio module that
interfaced to the low-power chipset. Tom Burd (who designed the radio receiver
module), Andy Burstein (who designed the SRAM), and Shankar Naraya
naswamy (responsible for the pen interface) directly contributed to the design of
the chipset. Of critical importance was the low-power cell-library that was largely
developed by Tom Burd and Andy Burstein. Brian Richards provided valuable sug
gestions concerning the chip designs and Roger Doering, Susan Mellers, and Ken
x
Lutz setup and supported the infrastructure for designing and testing boards. Fred
Burghardt, Brian Richards, and Shankar Narayanaswamy designed the basesta
tion software and applications. For the video chipset, Ian O'Donnell prototyped
the logic to verify the modified NTSC timing suggested by Ken Nishimura. Cor
mac Conroy and Robert Neff provided valuable suggestions on the DAC design.
Prof. Mark Horowitz of Stanford university provided us with a modified version
of IRSIM which we used extensively for power estimation. Finally, Tom Looka
baugh and Prof. Eve Riskin provided the source code for VQ which was used for
the InfoPad video demonstration.
Of key importance was the support obtained from our Government and
Industrial sponsors. The primary funding for the work described here was from
the Computer Information Systems Technology Office of ARPA. In particular, the
Deputy Office Director, John Toole gave us the freedom to redirect our efforts
into a major activity focussed on low power design and Program Manager, Bob
Parker, has continued w give us the flexibility to follow up promising research
areas and John Hoyt of the Justice department who has always been available to
help in not only the administrative aspects of our project, but in the technical
areas as well. Also, provided by ARPA support was access to the MaS IS fast
turnaround implementation service of the Information Science Institute of the
University of Southern California which was critical in aIlowing to tryout many
new ideas in circuit design with a minimum level of overhead.
LOW POWER DIGITAL CMOS DESIGN