Table Of Content

2 Available at Fa org ee “a ~N y oMev ) sf www.ElsevierComputerScience.com JOURNAL OF “ ¢.} i 4d d ‘a | SYSTEMS POWERED BY SCIENCE G@oinecre ARCHITECTURE ELSEVIER 49 (2 003) 663-665 formance levelopment Maced Drechsler, R.. W Gunther Linhard Angst tists I Mart inez, J ind H. ¢ jall, Arcl ea and 1} " wbdihl le COMaADOOTTA a see Dustdar rigo M.J Meneses video coding jeorge A.D see ( hi Evolutions in iOokhale M see Wolinsh network-based iO1 ve, R see Mermer sreen Pp see Edwards M P. El sand Z. Peng, Modeling and sunther W see Drechsler R verinica t ion of embedded systems sutiérrez E., O Plata ind E.l Zapat i Opti parallel i Petri net presentatic yn $71 miz ation i ques lor irregular Idd rea"u ctit ons 622 1/8 : I! nit mi itt er 2003 Elsevier B.V All rights re erved i: 10.1016/S1383-7621(03)00181-4 J urna McCabe, K.. see Wolinski, ¢ Hartenste! see Becker, J Mendias, J.M., see Molina, M.4 Hermida, R., see Molina, M.( Meneses, J.M., see Garrido, M.J Hiasat, A. and A. Sweidan, Residue number Mermer, ¢ D. Kim, S.G. Berg, R. Gove and unary converter for the moduli set Y. Kim, Use of embedded DRAMs in video | and image computing Loh, P.K.K Mohr, B.. see Wolf, I Molina, M.¢ J.M. Mendias and R Hermida Bernaschi Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources Montuno, D.Y., see Aweya, J reconfiguration Mory, E., see Bourgeois, J VLSI/WSI arrays Jimenez, M., see Garrido, M Nedjah, N. and L. de Macedo Mourelle, Fast Jozwiak, | Edwards, M reconfigurable systolic hardware for modular Jozwiak, | ind A. Chojnacki Effective and multiplication and exponentiation Pat 396 efficient FPGA synthesis through general Nunez, A., see Theelen, B.D 619 639 functional decomposition Jozwiak l 4. Slusarczyk and A. Chojnacki Ouellette, M Fast and compact sequential circuits for the FPGA-based reconfigurable systems Pelkonen, A., see Masselos, K Juurlink, B eresiz, D Peng, Z.. see Cortés, L.A Pineiro, J.-A., see Piso, D Kannan, R Bartos An optical Piso, D., J.-A. Pineiro and J.D Bruguera switching ure for hierarchical group Analysis of the impact of different methods communication for division/square root computation in the Kim, D Merme performance of a superscalar microprocessor Kim, J., see Cha, H Plata, O., see Gutiérrez, FE Kim, Y., see Mermer, ¢ Podhorszki, N see Vajda, I Koelma, D., see Seinstra, F.J Postula, A see Leung, S Krasniewski \ Evaluation of delay fault testability of LUTs for the enhancement of ipplication-dependent testing of FPGAs Quick P see I gan, ¢ K.uchcinski K nd ¢ Wolinski Global ipproach to assignment and scheduling of Radlinski, M.A., see Chidester, M.¢ complex behaviors based on HCDG Ray, S., see Kannan, R and constraint programming Reyes Suarez. V.V.. see Theelen, B.D Robles, A., see Martinez, J.¢ Larrea, M On the weakest failure « hard agreement problems San Millan, E., | Entrena, J.A. Espejo and Lauria, M., see Bernaschi, M I opez Theoretical comparison between Leung, S. and A. Postula Functionally parti- quential redundancy addition and remov: tioned module-based programmable architec and retiming optimization techniques 579 54] ture for wireless base-band processing Sanz, C., see Garrido, M.J 64] 661 Linhard, L., see Drechsler, R Seinstra, F.J. and D. Koelma Incorporating Loh, P.K.K. and W.J. Hsu, | ault-tolerance memory layout in the modeling of message Complet Josephus Cubes passing programs San Millan, I Skliarova, |. and A.B. Ferrari The design and Martinez, J.¢ implementation of a reconfigurable processor for problems of combinatorial computation Martinez, J.C., J. Flich, A. Robles, P. Lopez and Slusarczyk, A., see Jozwiak, | J. Duato, Supporting adaptive routing in IBA Spies, F., see Bourgeois, J switcne Srikanthan, T., see Jigang, W Masselos, K Pelkonen, M. ¢ Steven, I see f gan ( Blionas -alization wireless multimedia Steven, G see Egan, ¢ communication stem on reconfigurable Stevens, M.P.J., see Theelen, B.D platform Sweidan, A see Hiasat, A {uthor index | Journal of Systems Architecture 49 (2003 ) 663-665 Theelen, B.D., A.C. Verschueren, V.V. Reyes Wijshoff, H.A.G., see Cheresiz, D Suarez, M.P.J. Stevens and A. Nunez, A Wolf, F. and B. Mohr, Automatic performance scalable single-chip multi-processor architec- analysis of hybrid MPI/OpenMP applications ture with on-chip RTOS kernel 619-639 Wolinski, ¢ M. Gokhale and K. McCabe Polymorphous fabric-based systems: Model Uhl, A., see Feil, M 15-87 tools, applications Wolinski, C., see Kuchcinski, K Vajda, F. and N. Podhorszki, Parallel, distrib uted and network-based processing 61-62 = re J.- ( see Chen. H.-€ Vassiliadis, S., see Cheresiz, D 599-6] Yen - : i Verschueren, A.C., see Theelen, B.D 619-639 Vintan, L., see Egan, ¢ 557-570 Zapata, E.L., see Gutiérrez, f Available at www.ElsevierComputerScience.com JOURNAL OF SYSTEMS , POWERED BY science (oecrs ARCHITECTURE ELSEVIER Journal of Systems Architecture 49 (2003) 667-668 Subject index to volume 49 (2003) Fault-tolerance Fault-tolerant routing Formal verification FPGA FPGAs FPGA systems Greedy algorithm H.263 multiprocessors 3 Hardware kernel Hardware template High level synthesis High performance computing ation primitives ‘ Hypercube InfiniBand Information-drivet ipplications Instruction set Intellectual propert Interconnection net Irregular Latency Learning vecto oad balance Low bit-rat hit radable VLSI/WSI arra ” ediaprocessors MIMD architecture Mobile clients Mobile collaborative Model checking Modeling Montgomery algorithn Motion compensatior Motion estimation MPI Multimedia applications Multimedia streaming $ - see front matter 2003 Elsevier B.V. All rights reserved doi: 10.1016/S1383-7621(03)00182-6 Journal of Systems Architecture 49 (2003 ) 667-668 Multiple precis specificatic 305 Retiming Multiple ul sculion RISC Multiplicat ‘ RSA-cryptosystems Multi-processor Run-time configuration Multi-taskin Scalable content Sequential circuits SimpleScalar Skeletons Software architecture Square root State assignment Structured parallel programming models Parallel Superscalar processors Parallel mr ; System area networks Parallel programmi System-on-chip Partitioning Systems-on-a-chip Performanc Poeer formeann c TCP window control P» ertfoor rmraann Technology mapping Terminating reliable broadcast Testability evaluation Testing Thread speculation T'wo-level adaptive branch prediction User interface Video coding Virtual addressing VLSI design and verification Wavelet packets Wireless networks