Guide to Computer Processor Architecture: A RISC-V Approach, with High-Level Synthesis PDF
Preview Guide to Computer Processor Architecture: A RISC-V Approach, with High-Level Synthesis
Undergraduate Topics in Computer Science Bernard Goossens Guide to Computer Processor Architecture A RISC-V Approach, with High-Level Synthesis Undergraduate Topics in Computer Science Series Editor Ian Mackie, University of Sussex, Brighton, UK Advisory Editors Samson Abramsky , Department of Computer Science, University of Oxford, Oxford, UK ChrisHankin ,DepartmentofComputing,ImperialCollegeLondon,London,UK Mike Hinchey , Lero—The Irish Software Research Centre, University of Limerick, Limerick, Ireland Dexter C. Kozen, Department of Computer Science, Cornell University, Ithaca, NY, USA Andrew Pitts , Department of Computer Science and Technology, University of Cambridge, Cambridge, UK HanneRiisNielson ,DepartmentofAppliedMathematicsandComputerScience, Technical University of Denmark, Kongens Lyngby, Denmark StevenS.Skiena,DepartmentofComputerScience,StonyBrookUniversity,Stony Brook, NY, USA Iain Stewart , Department of Computer Science, Durham University, Durham, UK Joseph Migga Kizza, College of Engineering and Computer Science, The University of Tennessee-Chattanooga, Chattanooga, TN, USA ‘Undergraduate Topics in Computer Science’ (UTiCS) delivers high-quality instructional content for undergraduates studying in all areas of computing and information science. From core foundational and theoretical material to final-year topics and applications, UTiCS books take a fresh, concise, and modern approach and are ideal for self-study or for a one- or two-semester course. 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Bernard Goossens Guide to Computer Processor Architecture A RISC-V Approach, with High-Level Synthesis 123 Bernard Goossens UniversitédePerpignan Perpignan, France ISSN 1863-7310 ISSN 2197-1781 (electronic) Undergraduate Topics inComputer Science ISBN978-3-031-18022-4 ISBN978-3-031-18023-1 (eBook) https://doi.org/10.1007/978-3-031-18023-1 ©TheEditor(s)(ifapplicable)andTheAuthor(s),underexclusivelicensetoSpringerNature SwitzerlandAG2023 Thisworkissubjecttocopyright.AllrightsaresolelyandexclusivelylicensedbythePublisher,whether thewholeorpartofthematerialisconcerned,specificallytherightsoftranslation,reprinting,reuseof illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmissionorinformationstorageandretrieval,electronicadaptation,computersoftware,orbysimilar ordissimilarmethodologynowknownorhereafterdeveloped. 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ThisSpringerimprintispublishedbytheregisteredcompanySpringerNatureSwitzerlandAG Theregisteredcompanyaddressis:Gewerbestrasse11,6330Cham,Switzerland Preface Processor Architecture: A Do-It-Yourself Approach Thisbookisanewtextbookonprocessorarchitecture.Whatisnewisnotthetopic, even though actual multicore and multithreaded designs are depicted, but the way processor architecture is presented. This book can be related to the famous Douglas Comer textbook on Operating System (OS) [1,2]. As Douglas Comerdidto present thedesign ofan OS,I usea DIY approach to present processor designs. In his book, Douglas Comer builds afull OS from scratch,withC source code. Inthepresentbook,Iaimtomakeyoubuildyourownprocessors,alsofromscratch and also with C source code. All you need is a computer, an optional development board, and a set offreely available softwares to transform C programs into equivalent FPGA implementa- tions (field-programmable gate array). If you don’t have a development board, you can still simulate the processors presented in the book though. In the 70s (of the twentieth century of course), it became possible for a single persontobuildafullOS(KennethL.ThompsoncreatedUnixin1970),andbetter than that, to write a How-To book giving a complete recipe to implement a Unix-like OS (Douglas Comer published Xinu in 1984). Two improvements in computer hardware and software made it eventually feasible: the availability of personal computers and the C programming language. They give the full access to the hardware. Nowadays, an FPGA plays the role of the personal computer of the 70s: It givesaccesstothelogicgates.TheHigh-LevelSynthesistool(HLS)playstherole of the C compiler of the 70s: It gives access to the FPGA through a high-level language. v vi Preface RISC-V Open-Source Processor Designs TheDouglasComerbookexplainedhowtobuildanOSusingaself-madeexample named Xinu. Even though Xinu was claimed not to be Unix (Xinu is a recursive acronymmeaning“XinuIsNotUnix”),itwouldbehaveverylikely,givingthereader and implementer the opportunity to compare his/her own realization to the Unix reference. Inthe same idea, Ihave chosen areference processortobe able to comparethe FPGA-based processor proposed in the book to real RISC-V industrial products. RISC-Visanopen-sourceInstructionSetArchitecture(ISA),whichmeansthat youcanbuildaRISC-Vprocessor,useit,andevensellit,withoutthepermissionof any computer constructor. It would not be so for Intel’s X86 or ARM’s v7 or v8. Moreover, RISC-V defines multiple gigogne ISA subsets. A processor may implement any level of the matriochka organization of the ISA. In this book, you will implement one of the most basic subsets, namely RV32I (a set of machine instructions to compute on 32-bits integer words). But you will know enough to be able to expand your processor to 64-bits words, to add a floating-point computation subset and many more, according to the RISC-V specification [3]. Moreover, the subset you will be implementing is enough to boot an OS like Linux (which is not part of this book though). A Very Practical Introduction to Computer Architecture for Undergraduate Students This book is also a very practical introduction to computer architecture. It can be seen as an application of more complete reference books of the domain (see for examplethemostrecenteditionsofthefamousbooksoncomputerarchitectureby J. L. Hennessy and D. A. Patterson [4, 5]). Along the chapters, you will implement different processor organizations: (cid:129) Basic(e.g.,Intel4004.TheIntel4004wasthefirstmicroprocessorintroducedin 1971, i.e., the first processor to fit in a single integrated circuit.) [6, 7]. (cid:129) Slightly pipelined (e.g., RISC-I. The RISC-I processor was the first pipelined microprocessor, introducing the Reduced Instruction Set Computer or RISC concept in 1980.) [8]. (cid:129) Moderately pipelined (e.g., MIPS. The MIPS or microprocessor without Inter- locked PipelineStages was a concurrentof RISC-I, adding techniques to better fill the pipeline.) [9]. (cid:129) Pipeline for multicycle operations (or multicycle pipeline). This is an enhancement ofthe pipeline tohandle multiplecycle memory accesses, integer multiplication and division, or floating-point operations. Preface vii (cid:129) Multiple threads (e.g., SMT. The SMT or simultaneous multithreading is an enhancementtosharethepipelinebetweenmultiplethreadsandso,fillitbetter. This technique is also known as Hyper Threading, as named by Intel.) [10]. (cid:129) Multiple cores (e.g., IBM Power-4. The Power-4 was the first multicore processor, introduced in 2001. It had two cores.) [11]. Even though you stay at the simulation level because you do not have a development board, the designs have been tested on an FPGA and they respect hardware constraints. A Teaching Tool for Instructors With a GitHub Support All the processors designed in this book are provided as open-source projects (either to build the simulation only version or the full FPGA-based projects to be tested on a Xilinx-based development board) available in the goossens-book- ip-projects repository of the https://github.com/goossens-springer github. AfullchapterofthebookisdevotedtotheinstallationoftheRISC-Vtools(gnu toolchainincludingtheRISC-Vcross-compiler,spikesimulator,gdbdebugger,and the RISC-V-tests official test and benchmarks suite provided by the RISC-V international organization (https://riscv.org/). The implementations proposed in the book are compared from a performance perspective, applying the famous Hennessy–Patterson “quantitative approach” [4]. The book presents an adaptation of a benchmark suite to the development board no-OS environment. The same benchmark suite is used throughout the book to test and compare the performance of the successive designs. These comparisons highlight the cycle per instruction (CPI) term in the processor performance equation. Such comparisons based on really implemented softcores are more convincing for students than similar evaluations relying on simulation with no real hardware constraints. The different microarchitectures described in the book introduce the general concepts related to pipelining: branch delay and cancelation, bypassing in-flight values, load delay, multicycle operators, and more generally, filling the pipeline stages. The chapter devoted to the RISC-V RV32I is also an introduction to assembly programming. RISC-V codes are obtained from the compilation of C patterns (expressions, tests, loops, and functions) and analyzed. Throughoutthebook,someexercisesareproposedwhichcanserveassemester projects, like extending the given implementations to the RISC-V M or F ISA subsets. viii Preface Such a box signals some experimentation the reader can do from the resources available in the goossens-book-ip-projects/2022.1 folder in the https://github.com/goossens-springer github. TheVitis_HLSprojectsarepre-built(youjustneedtoselectthetestbench file you want to use for your IP simulation) (IP means Intellectual Property, i.e., your component). TheVivadoprojectsarealsopre-builtwithdriverstodirectlytestyourIPs on the development board. The expected results are in the book. A Practical and Detailed Introduction to High-Level Synthesis and to RISC-V for FPGA Engineers The book is a very detailed introduction to High-Level Synthesis. HLS will cer- tainly become the standard way to produce RTL, progressively replacing Verilog/VHDL, asin the 50s and 60s, high-level languagesprogressivelyreplaced the assembly language. Chapter 2 of the book presents the Xilinx HLS environment in the Vitis tool suite.BasedonanIPimplementationexample,ittravelsthroughallthestepsfrom HLStotheXilinxIPintegratorVivadoandtheXilinxVitisIDE(IntegratedDesign Environment) to upload the bitstream on the FPGA. The book explains how to implement, simulate, synthesize, run on FPGA, and even debug HLS softcore projects without the need to go down to Verilog/VHDL or chronograms. HLS is today a matured tool which gives engineers the ability to quickly develop FPGA prototypes. The development of a RISC-V processor in HLS is a one engineer-month duty, when implementing an ARM processor in VHDLwasmorelikeayearjob,thankstoHLSandthankstothesimplicityofthe RV32I instruction nucleus in the RISC-V ISA. The book explains the major pragmas used by the HLS synthesizer (ARRAY PARTITION, DEPENDENCE, INTERFACE, INLINE, LATENCY, PIPELINE, UNROLL). Part I of the book concerns individual IPs, and Part II is devoted to System- on-Chips built from multiples core and memory IPs interconnected by an AXI interconnection component. The book is also an introduction to RISC-V. A full chapter is devoted to the presentation of the RV32I ISA. ThemarketgrowthofRISC-Vprocessorsisalreadyimpressiveinthedomainof embedded computing. The future of RISC-V might be the same as what was the progressionofUnixinthedomainofoperatingsystems.Atleast,thefirststepsare comparable, with a no-constructor and open-source philosophy. Preface ix What the Book Does Not Contain However,thisbookdoesnotcontainanyimplementationofthetechniquesfoundin the most advanced processors, like superscalar execution, out-of-order execution, speculation, branch prediction, or value prediction (however, these concepts are at least defined). The reason is that these microarchitectural features are too complex to fit in a small FPGA like the one I used. For example, a cost-effective out-of-order design requires a superscalar pipeline, an advanced branch predictor, and a hierarchical memory altogether. Thereisnoimplementationofadvancedparallelmanagementunitslikeashared memory management (i.e., cache coherency) for the same reason. Thebookdoesnotincludeanyimplementationofcachesorcomplexarithmetic operators(multiplication,division,orfloating-pointunit).TheycanfitontheFPGA (atleastinasinglecoreandsinglethreadprocessor).Theyareleftasanexercisefor the reader. An Organization in Two Parts: Single Core Designs, Multiple Core Designs Thebookisdividedintotwopartsand14chapters,includinganintroductionanda conclusion.PartI,fromChaps.1to10,isdevotedtosinglecoreprocessors.PartII, from Chaps. 11 to 14, presents some multicore implementations. Chapter1istheintroduction.ItpresentswhatanFPGAisandhowHLSworks to transform a C program into a bitstream to configure the FPGA. The two following chapters give the necessary indications to build the full environment used in the book to develop the RISC-V processors. Chapter 2 is related to the Xilinx Vitis FPGA tools (the Vitis_HLS FPGA synthesizer, the Vivado FPGA integrator, and the Vitis IDE FPGA programmer). Chapter 3 presents the RISC-V tools (the Gnu toolchain, the Spike simulator, and the OpenOCD/gdb debugger), their installation, and the way to use them. Chapter4presentstheRISC-Varchitecture(moreprecisely,theRV32IISA)and the assembly language programming. Chapter5showsthethreemainstepsinbuildingaprocessor:fetching,decoding, and executing. The construction is incremental. ThegeneralprinciplesofHLSprogramming,incontrasttoclassicprogramming, are explained in the first section of Chap. 5. Chapter6completeschapterfivewiththeadditionofadatamemorytofulfillthe firstRISC-VprocessorIP.Theimplementedmicroarchitecturehasthemostsimple non-pipelined organization.
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