Digital Signal Processing with Field Programmable Gate Arrays

788 Pages·2007·11 MB·English

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Uwe Meyer-Baese
Digital Signal Processing
with Field Programmable
Gate Arrays
ThirdEdition
With359Figuresand98Tables
BookwithCD-ROM
123
Dr.UweMeyer-Baese
FloridaStateUniversity
CollegeofEngineering
DepartmentElectrical&ComputerEngineering
PottsdamerSt.2525
Tallahassee,Florida32310
USA
E-Mail:[email protected]
Originallypublishedasamonograph
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ISBN 978-3-540-72612-8 SpringerBerlinHeidelbergNewYork
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is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation,
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To my Parents,
Anke and Lisa
Preface
Field-programmablegatearrays(FPGAs)areonthe vergeofrevolutionizing
digitalsignalprocessinginthemannerthatprogrammabledigitalsignalpro-
cessors (PDSPs) did nearly two decades ago. Many front-end digital signal
processing (DSP) algorithms, such as FFTs, FIR or IIR filters, to name just
a few, previously built with ASICs or PDSPs, are now most often replaced
by FPGAs. Modern FPGA families provide DSP arithmetic support with
fast-carry chains (Xilinx Virtex, Altera FLEX) that are used to implement
multiply-accumulates(MACs)athighspeed,withlowoverheadandlowcosts
[1]. Previous FPGA families have most often targeted TTL “glue logic” and
did not have the high gate count needed for DSP functions. The efficient
implementation of these front-end algorithms is the main goal of this book.
At the beginning of the twenty-first century we find that the two pro-
grammable logic device (PLD) market leaders (Altera and Xilinx) both re-
portrevenuesgreaterthanUS$1 billion.FPGAs haveenjoyedsteady growth
of more than 20% in the last decade, outperforming ASICs and PDSPs by
10%. This comes from the fact that FPGAs have many features in com-
mon with ASICs, such as reduction in size, weight, and power dissipation,
higher throughput, better security against unauthorized copies, reduced de-
vice and inventory cost, and reduced board test costs, and claim advantages
over ASICs, such as a reduction in development time (rapid prototyping),
in-circuit reprogrammability, lower NRE costs, resulting in more econom-
ical designs for solutions requiring less than 1000 units. Compared with
PDSPs,FPGAdesigntypicallyexploitsparallelism,e.g.,implementingmulti-
plemultiply-accumulatecallsefficiency,e.g.,zeroproduct-termsareremoved,
and pipelining, i.e., each LE has a register, therefore pipelining requires no
additional resources.
Another trend in the DSP hardware design world is the migration from
graphical design entries to hardware description language (HDL). Although
manyDSPalgorithmscanbedescribedwith“signalflowgraphs,”ithasbeen
found that “code reuse” is much higher with HDL-based entries than with
graphical design entries. There is a high demand for HDL design engineers
and we already find undergraduateclassesabout logic designwith HDLs [2].
UnfortunatelytwoHDL languagesarepopulartoday.TheUSwestcoastand
Asia area prefer Verilog, while US east coast and Europe more frequently
VIII Preface
use VHDL. For DSP with FPGAs both languages seem to be well suited,
althoughsome VHDL examplesarea little easiertoreadbecause ofthe sup-
portedsignedarithmetic andmultiply/divide operationsinthe IEEEVHDL
1076-1987 and 1076-1993 standards. The gap is expected to disappear after
approval of the Verilog IEEE standard 1364-1999, as it also includes signed
arithmetic.Other constraintsmayinclude personalpreferences,EDAlibrary
and tool availability, data types, readability, capability, and language exten-
sions using PLIs, as well as commercial, business, and marketing issues, to
name just a few [3]. Tool providers acknowledge today that both languages
havetobesupportedandthisbookcoversexamplesinbothdesignlanguages.
Wearenowalsointhefortunatesituationthat“baseline”HDLcompilers
are availablefrom differentsources atessentially no costfor educationaluse.
We take advantage of this fact in this book. It includes a CD-ROM with
Altera’s newestMaxPlusIIsoftware,whichprovidesa complete setof design
tools,fromacontent-sensitiveeditor,compiler,andsimulator,toabitstream
generator. All examples presented are written in VHDL and Verilog and
should be easily adapted to other propriety design-entry systems. Xilinx’s
“FoundationSeries,”ModelTech’sModelSimcompiler,andSynopsysFC2or
FPGA Compiler should work without any changes in the VHDL or Verilog
code.
Thebookisstructuredasfollows.Thefirstchapterstartswithasnapshot
of today’s FPGA technology,and the devices and tools used to design state-
of-the-art DSP systems. It also includes a detailed case study of a frequency
synthesizer,includingcompilationsteps,simulation,performanceevaluation,
power estimation, and floor planning. This case study is the basis for more
than 30 other design examples in subsequent chapters. The second chapter
focuses on the computer arithmetic aspects, which include possible number
representationsforDSPFPGAalgorithmsaswellasimplementationofbasic
buildingblocks,suchasadders,multipliers,orsum-of-productcomputations.
Attheendofthechapterwediscusstwoveryusefulcomputerarithmeticcon-
cepts for FPGAs: distributed arithmetic (DA) and the CORDIC algorithm.
Chapters 3 and 4 deal with theory and implementation of FIR and IIR fil-
ters. We will review how to determine filter coefficients and discuss possible
implementationsoptimizedforsizeorspeed.Chapter5coversmanyconcepts
usedinmultiratedigitalsignalprocessingsystems,suchasdecimation,inter-
polation, and filter banks. At the end of Chap. 5 we discuss the various pos-
sibilities for implementing wavelet processors with two-channel filter banks.
InChap.6,implementationofthemostimportantDFTandFFTalgorithms
is discussed. These include Rader, chirp-z,and Goertzel DFT algorithms,as
well as Cooley–Tuckey, Good–Thomas, and Winograd FFT algorithms. In
Chap. 7 we discuss more specialized algorithms, which seem to have great
potential for improved FPGA implementation when compared with PDSPs.
These algorithms include number theoretic transforms, algorithms for cryp-
tography and errorcorrection, and communication system implementations.
Preface IX
The appendix includes an overviewof the VHDL and Verilog languages,the
examples in Verilog HDL, and a short introduction to the utility programs
included on the CD-ROM.
Acknowledgements. ThisbookisbasedonanFPGAcommunicationssystemdesign
classItaughtforfouryearsattheDarmstadtUniversityofTechnology;myprevious
(German)books[4,5];andmorethan60MastersthesisprojectsIhavesupervised
in the last 10 years at Darmstadt University of Technology and the University
of Florida at Gainesville. I wish to thank all my colleagues who helped me with
critical discussions in the lab and at conferences. Special thanks to: M. Acheroy,
D.Achilles,F.Bock,C.Burrus,D.Chester,D.Childers,J.Conway,R.Crochiere,
K.Damm,B.Delguette,A.Dempster,C.Dick,P.Duhamel,A.Drolshagen,W.En-
dres, H.Eveking,S.Foo, R.Games, A.Garcia, O. Ghitza, B. Harvey,W.Hilberg,
W.Jenkins,A.Laine,R.Laur,J.Mangen,J.Massey,J.McClellan,F.Ohl,S.Orr,
R. Perry, J. Ramirez, H. Scheich, H. Scheid, M. Schroeder, D. Schulz, F. Simons,
M. Soderstrand,S.Stearns,P.Vaidyanathan,M.Vetterli,H.Walter,andJ.Wiet-
zke.
Iwouldliketothankmystudentsfortheinnumerablehourstheyhavespentim-
plementingmyFPGAdesignideas.Specialthanksto:D.Abdolrahimi,E.Allmann,
B. Annamaier, R. Bach, C. Brandt, M. Brauner, R. Bug, J. Burros, M. Burschel,
H. Diehl, V. Dierkes, A. Dietrich, S. Dworak, W. Fieber, J. Guyot, T. Hatter-
mann,T. H¨auser,H.Hausmann,D.Herold, T.Heute,J. Hill,A. Hundt,R.Huth-
mann, T. Irmler, M. Katzenberger, S. Kenne, S. Kerkmann, V. Kleipa, M. Koch,
T. Kru¨ger, H. Leitel, J. Maier, A. Noll, T. Podzimek, W. Praefcke, R. Resch,
M. R¨osch, C. Scheerer, R. Schimpf, B. Schlanske, J. Schleichert, H. Schmitt,
P. Schreiner, T. Schubert, D. Schulz, A. Schuppert, O. Six, O. Spiess, O. Tamm,
W. Trautmann, S.Ullrich, R.Watzel, H. Wech,S. Wolf, T. Wolf, and F. Zahn.
For the English revision I wish to thank my wife Dr. Anke Meyer-B¨ase, Dr.
J. Harris, Dr. Fred Taylor from the University of Florida at Gainesville, and Paul
DeGroot from Springer.
For financial support I would like to thank the DAAD, DFG, the European
Space Agency,and the Max Kade Foundation.
Ifyoufindanyerrataorhaveanysuggestionstoimprovethisbook,please
contact me at [email protected] through my publisher.
Tallahassee, May 2001 Uwe Meyer-Ba¨se
Preface to Second Edition
Aneweditionofabookisalwaysagoodopportunitytokeepupwiththelat-
est developments in the field and to correctsome errorsin previous editions.
To do so, I have done the following for this second edition:
• Set up a web page for the book at the following URL:
http://hometown.aol.de/uwemeyerbaese
The site has additional information on DSP with FPGAs, useful links,
andadditionalsupportforyourdesigns,suchascodegeneratorsandextra
documentation.
• Correctedthemistakesfromthefirstedition.Theerrataforthefirstedition
canbedownloadedfromthebookwebpageorfromtheSpringerwebpage
at www.springer.de,by searching for Meyer-Baese.
• A total of approximately 100 pages have been added to the new edition.
The major new topics are:
– The design of serial and array dividers
– The description of a complete floating-point library
– A new Chap. 8 on adaptive filter design
• Altera’s current student version has been updated from 9.23 to 10.2 and
all design examples, size and performance measurements, i.e., many ta-
bles and plots have been compiled for the EPF10K70RC240-4 device
that is on Altera’s university board UP2. Altera’s UP1 board with the
EPF10K20RC240-4has been discontinued.
• Asolutionmanualforthefirstedition(withmorethan65exercisesandover
33 additionaldesignexamples)is availablefromAmazon.Some additional
(over 25) new homework exercises are included in the second edition.
Acknowledgements. I would like tothank mycolleagues and studentsfor thefeed-
back to the first edition. It helped me to improve the book. Special thanks to:
P.Ashenden,P.Athanas,D.Belc,H.Butterweck,S.Conners,G.Coutu,P.Costa,
J. Hamblen,M. Horne, D.Hyde,W. Li, S. Lowe, H.Natarajan, S. Rao, M. Rupp,
T. Sexton,D. Sunkara,P.Tomaszewicz, F. Verahrami, and Y. Yunhua.
From Altera, I would like to thank B. Esposito, J. Hanson, R. Maroccia,
T.Mossadak,andA.Acevedo(nowwithXilinx)forsoftwareandhardwaresupport
and thepermission to includedatasheets and MaxPlus II on the CD of thisbook.
Frommypublisher(Springer-Verlag)IwouldliketothankP.Jantzen,F.Holz-
warth, and Dr. Merkle for their continuoussupport and help over recent years.