Digital Computer Arithmetic Datapath Design Using Verilog HDL: CD-ROM Included

184 Pages·2004·9 MB·English

by  James E. Stine (auth.)

DIGITAL COMPUTER
ARITHMETIC DATAPATH DESIGN
USING VERILOG HDL
DIGITAL COMPUTER
ARITHMETIC DATAPATH DESIGN
USING VERILOG HDL
J ames E. Stine
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
Library of Congress Cataloging-in-Pnblication Data
Digital Computer Arithmetic Datapath Design Using Verilog HDL
James E. Stine
Additioual material to this book cau be dowuloaded from http://extras.spriuger.com.
ISBN 978-1-4613-4725-5 ISBN 978-1-4419-8931-4 (eBook)
DOI 10.1007/978-1-4419-8931-4
Copyright © 2004 by Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers in 2004
Softcover reprint ofthe hardcover Ist edition
AlI rights reserved. No part of this work may be reproduced, stored in a retrieval
system, or transmitted in any form or by any means, electronic, mechanical,
photocopying, microfilming, recording, or otherwise, without prior written
permission from the Publisher, with the exception of any material supplied
specificalIy for the purpose of being entered and executed on a computer system,
for exclusive use by the purchaser of the work.
Printed on acid-free paper.
Contents
Preface ix
l. MOTIVATION 1
1.1 Why Use Verilog HDL? 1
1.2 Whatthis bookisnot : Main Objective 2
1.3 DatapathDesign 3
2. VERILOG ATTHERTL LEVEL 7
2.1 Abstraction 7
2.2 Naming Methodology 10
2.2.1 Gate Instances 11
2.2.2 Nets 12
2.2.3 Registers 12
2.2.4 Connection Rules 13
2.2.5 Vectors 14
2.2.6 Memory 14
2.2.7 NestedModules 15
2.3 ForceFeeding Verilog : the Test Bench 16
2.3.1 TestBenches 18
2.4 OtherOdds and Ends within Verilog 19
2.4.1 Concatenation 19
2.4.2 Replication 21
2.4.3 Writing to Standard Output 21
2.4.4 StoppingaSimulation 21
2.5 Timing:ForWhom the Bell Tolls 22
2.5.1 Delay-basedTiming 22
2.5.2 Event-BasedTiming 23
VI DIGITALCOMPUTERARITHMETICDATAPATHDESIGN
2.6 SynopsysDesignWareIntellectualProperty (IP) 24
2.7 Verilog 2001 24
2.8 Summary 26
3. ADDITION 27
3.1 HalfAdders 28
3.2 Full Adders 28
3.3 Ripple Carry Adders 30
3.4 RippleCarry AdderlSubtractor 31
3.4.1 Carry LookaheadAdders 34
3.4.1.1 BlockCarry LookaheadGenerators 36
3.5 Carry Skip Adders 40
3.5.1 Optimizing theBlockSize to ReduceDelay 42
3.6 Carry SelectAdders 43
3.6.1 Optimizing the BlockSize toReduceDelay 46
3.7 Prefix Addition 47
3.8 Summary 52
4. MULTIPLICATION 55
4.1 Unsigned Binary Multiplication 56
4.2 Carry-SaveConcept 56
4.3 Carry-SaveArray Multipliers (CSAM) 60
4.4 Tree Multipliers 61
4.4.1 Wallace Tree Multipliers 61
4.4.2 DaddaTree Multipliers 65
4.4.3 ReducedArea (RA) Multipliers 68
4.5 TruncatedMultiplication 71
4.6 Two's ComplementMultiplication 78
4.7 Signed-DigitNumbers 82
4.8 Booth's algorithm 86
4.8.1 BitwiseOperators 87
4.9 Radix-4 Modified Booth Multipliers 89
4.9.1 SignedRadix-4 Modified Booth Multiplication 91
4.10 FractionalMultiplication 92
4.11 Summary 93
Contents Vll
5. DIVISIONUSINGRECURRENCE 103
5.1 Digit Recurrence 104
5.2 QuotientDigit Selection 105
5.2.1 ContainmentCondition 106
5.2.2 Continuity Condition 106
5.3 On-the-Fly-Conversion 108
5.4 Radix 2Division 112
5.5 Radix 4Divisionwith a = 2 andNon-redundantResidual 115
5.5.1 RedundantAdder 118
5.6 Radix 4Division with a = 2and Carry-SaveAdder 119
5.7 Radix 16Division with TwoRadix 4OverlappedStages 122
5.8 Summary 126
6. ELEMENTARYFUNCTIONS 129
6.1 GenericTableLookup 131
6.2 ConstantApproximations 133
6.3 PiecewiseConstantApproximation 134
6.4 LinearApproximations 136
6.4.1 Round to NearestEven 138
6.5 BipartiteTableMethods 141
6.5.1 SBTM and STAM 142
6.6 Shift and Add: CORDIC 147
6.7 Summary 152
7. DIVISIONUSINGMULTIPLICATIVE-BASED
METHODS 161
7.1 Newton-RaphsonMethodfor ReciprocalApproximation 161
7.2 Multiplicative-DivideUsingConvergence 166
7.3 Summary 168
References 171
Index 179
Preface
Theroleofarithmeticindatapathdesign inVLSIdesign hasbeenincreasing
in importance over the last several years due to the demand for processors
that are smaller, faster, and dissipate less power. Unfortunately, this means
thatmany ofthese datapaths willbecomplex both algorithmically and circuit
wise. Asthecomplexity ofthechips increases, less importance will be placed
on understanding how a particular arithmetic datapath design is implemented
and more importance will be given to when a product will be placed on the
market. This is because many tools that are available today, are automated to
help thedigital system designer maximize their efficiently. Unfortunately, this
may lead toproblems whenimplementing particular datapaths.
The design of high-performance architectures is becoming more compli
cated because the level of integration that is capable for many of these chips
is in the billions. Many engineers rely heavily on software tools to optimize
their work, therefore, as designs are getting more complex less understanding
isgoinginto aparticular implementation because itcanbegenerated automati
cally. Although softwaretoolsareahighlyvaluable assettodesigner, thevalue
ofthese toolsdoes not diminish theimportance ofunderstanding datapath ele
ments. Therefore, adigital systemdesigner shouldbeawareofhowalgorithms
canbeimplemented fordatapath elements. Unfortunately, due tothecomplex
ity of some of these algorithms, it is sometimes difficult to understand how a
particular algorithm isimplemented without seeing theactual code.
The goalofthis textistopresentbasic implementations for arithmetic data
pathdesigns andthemethodology utilized tocreate them. There arenocontrol
modules, however, with proper testbench design it should be easy to verify
any of the modules created in this text. As stated in the text, this text is not
a book on the actual theory. Theory is presented to illustrate what choices
are made and why, however, a good arithmetic textbook is probably required
to accompany this text. Utilizing the Verilog code can be paramount along
with a textbook on arithmetic and architecture to make ardent strides towards
x DIGITALCOMPUTERARITHMETICDATAPATHDESIGN
understanding many of the implementations that exist for arithmetic datapath
design.
Wherever possible, structural models are implemented to illustrate the de
sign principles. The importance for each design is on the algorithm and not
the circuit implementation. Both algorithmic and circuit trade-offs should be
adhered towhenadesign isunderconsideration. The idea inthis textisimple
ment each design at the RTL level so that it may be possibly implemented in
many different ways(i.e. standard-cell orcustom-cell).
This text has been used partially as lecture notes for a graduate courses in
Advanced VLSI system design and High Speed Computer Arithmetic at the
Illinois Institute of Technology. Each implementation has been tested with
several thousand vectors, however, there may be a possibility that a module
might have a small error due to the volume of modules listed in this treatise.
Therefore, comments, suggestions, orcorrections arehighly encouraged.
I am grateful to many of my colleagues who have supported me in this
endeavor, asked questions, and encouraged me to continue this effort. In par
ticular,I thank Milos Ercegovac and MikeSchulte for support, advice, and in
terest. There aremanyinfluentialworksintheareaofcomputerarithmetic that
have spanned many years. The interested reader should consult frequent con
ference on arithmetic such as the IEEE Symposium on Computer Arithmetic,
International Conference on Application-Specific Systems, Architectures, and
Processors (ASAP), Proceedings ofthe Asilomar Conference onSignals, Sys
tems, and Computers, and the IEEE International Conference on Computer
Design (ICCD) among others.
I would also liketothank my students who helped withdebugging at times
as well general support: Snehal Ajmera, Jeff Blank, Ivan Castellanos, Jun
Chen, Vibhuti Dave, Johannes Grad, Nathan Jachimiec, Fernando Martinez
Vallina,and Bhushan Shinkre. In addition, a special thank you goes to Karen
Brenner atSynopsys, Inc. for supporting thebook as well.
I am also very thankful to the staff at Kluwer Academic Publishers who
have been tremendously helpful during the process of producing this book.
I am especially thankful to Alex Greene and Melissa Sullivan for patience,
understanding, and overall confidence in this book. I thank them for their
support ofme and myendeavors.
Last but not least, I wish to thank my wife, Lori, my sons, Justyn, Jordan,
Jacob, Caden, andmydaughterRachel whoprovidedmewithsupport inmany,
many waysincluding putting upwithme whileIspentcountless hours writing
the book.
J.E. Stine
xi
Synopsys and DesignWareare registered trademarks ofSynopsys, Inc.
Chapter 1
MOTIVATION
Verilog HDL is a Hardware Description Language (HDL) utilized for the
mode ling and simulation of digital systems. It is designed to be simple, intu
itive, and effective at multiple levels of abstraction in a standard textual format
for a variety of different tools [IEE95]. The Verilog HDL was introduced by
Phil Moorby in 1984 at the Gateway Design Automation conference. Verilog
HDL became an IEEE standard in 1995 as IEEE standard 1364-1995 [IEE95].
After the standardization process was complete and firmly established into the
design community, it was enhanced and modified in the subsequent IEEE stan
dard 1364-2001 [IEE01]. Consequently, Veri log HDL provides a fundamental
and rigorous mathematical formalistic approach to model digital systems.
The framework and methodology for modeling and simulation is the overall
goal of the Verilog HDL language. The main purpose of this language is to
describe two important aspects of its objective:
• Levels of System Specification -Describes how the digital system behaves
and the provides the mechanism that makes it work.
• System Specification Formalism - Designers can utilize abstractions to
represent their Very Large Scale Integration (VLSI) or digital systems.
1.1 Why Use Verilog HDL?
Digital systems are highly complex. At the most detailed level, VLSI de
signs may contain billions of elements. The Verilog language provides digital
designers with a means of describing a digital system at a wide range of levels
of abstraction. In addition, it provides access to computer-aided design tools
to aid in the design process at these levels.
The goal in the book is to create computer arithmetic datapath design and to
use Verilog to precisely describe the functionality of the digital system. Verilog
J. Stine, Digital Computer Arithmetic Datapath Design Using HDL
© Springer Science+Business Media New York 2004