Design of an IEEE compliant 32-bit floating point multiplier/accumulator

104 Pages·2015·2.74 MB·English

by  Richard J. Niescier

Lehigh University
Lehigh Preserve
Theses and Dissertations
1994
Design of an IEEE compliant 32-bit floating point
multiplier/accumulator
Richard J. Niescier
Lehigh University
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Niescier, Richard J., "Design of an IEEE compliant 32-bit floating point multiplier/accumulator" (1994).Theses and Dissertations.
Paper 253.
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AUTHOR:
J.
Niescier, Richard
TITLE:
Design of an IEEE
Compliant 32-Bit
, Floating p'oint
MultiplierlAccumulator
DATE: May 29,1994
Design of an IEEE Compliant 32-bit Floating Point Multiplier/Accumulator
by
Richard J. Niescier
AThesis
Presented to the Graduated and Research Committee
of Lehigh University
in Candidacy for the Degree of
Master of Science
in
Electrical and Computer Engineering Department
Lehigh University
May 16,1994

Acknowledgment
This thesis is dedicated to my mother and father for
their continual support for my educational pursuits.
iii
Table of Contents
Acknowledgment 111
Table ofContents iv
ListofFigures ~ v
ListofTables vii
Abstract 1
Chapter 1 Introduction 2
,
Chapter2 IEEEFloating PointStandard754 .4
Chapter3 System LevelDesign l.10
3.1 MantissaLogic 11
3.1.1 PartialProductAddition 11 ,
3.1.2 Accumulatoradd,final summation,normalizationandrounding 15
3.1.3 AccumulatorAlignment. 21
3.2 ExponentProcessing 27
3.3 ExceptionsProcessing .32
3.4 RoundingLogic .35
3.5 SignLogic .38
j,
Chapter4 CircuitD~sign 42
4.1 FullAdderDesign 43
4.2 FullAdderSimulation 44
4.3 BoothRecoderandPartialProductTree 54
4.4 PartialProductAdderTreeSimulation 63
4.5 Final74BitFastAdderDesign : , 66
4.5.1 RippleAdder 66
4.5.2 ManchesterAdder : 67
4.5.3 Carry-Skip Adder 68
4.5.4 CarryLookaheadAdder 69
4.5.5 CarrySelectAdder 70
4.5.6 FastAdderforthisDesign 71
4.6 Final74BitFastAdderSimulation 73
4.7 LeadingZero/OneDetectorDesign 77
4.8 LeadingZero/OneDetectorSimulation 79
4.9 LeftShifterlRightShifterDesign 84
4.10 LeftlRightShifterSimulations 85
Chapter 5 Conclusions 87
Chapter 6 References and Bibliography 90
Chapter7 Appendix 93
Chapter8 BriefBiography 94
iv
List of Figures
~
r.
FIGURE Functional Diagram ofthe Mantissa/AccumulatorProcessing unit. 23
FIGURE 2. Mantissainputlatches, boothrecoder and partialproduct adders 24
FIGURE 3. Fast Adder, Normalizer and Rounder 25
FIGURE4. Accumulator alignment, and 2's complementer 26
FIGURE 5. FunctionalDiagram ofthe Exponentprocessingunit.. .30
FIGURE 6. Top-Levelcircuitschematic ofthe ExponentProcessing Unit.. 31
FIGURE7. Top-Levelcircuitschematic ofthe ExceptionsProcessingUnit. .34
FIGURE8. Top-LevelCircuitSchematicfor the Rounding Determination Logic 37
FIGURE9. FunctionalDiagram ofthe sign/accumulatornegationlogic .40
FIGURE 10. Top-LevelCircuitSchematicofthe Sign and Accumulation negation
Logic 41
FIGURE 11. FullAdder, Version 1 46
,.
. FIGURE 12. Full Adder, Version 2 47
FIGURE 13. Full Adder, Version 3 48
FIGURE 14. 4-2 Adderimplementation using non-restring n-channel XOR gates .49
FIGURE 15. Simulationsofthefull adders, under0.9um nominal processing, 5.0volts..
50
FIGURE 16. Simulation ofFull Adders under 0.9um worstcase conditions, 4.5 volts. 51
FIGURE 17. Simulationsofthe FullAdders under0.9um bestcase conditions 5.5 volts.
52
FIGURE 18. Simulationsofthe FullAdders under0.6um HD, worstcase conditions,
3.0 volts 53
FIGURE 19. "L-tree" type partial producttree reduction using carry-save addercells.54
FIGURE 20. "V-Tree" partialproducttree reduction using carry-save adders with a 12
to 2compressor technique 55
FIGURE 21. 4-2 Adders shown with the carry propagation 56
FIGURE 22. Use of4-2 and 3-2 Adders to reduce 12 partialproducts to 2 57
FIGURE 23. WallaceTree implementationfor adding7 bits 58
FIGURE 24. Textual representation ofhow to reduce 13 partial products to 2 59
FIGURE 25. Blockdiagram ofthe reduction of 13 partialproducts to 2 60
FIGURE 26. Textual representation ofhow to reduce 24partialproducts to 2 61
FIGURE 27. Block Diagram ofhow to reduce 24partialproducU? to 2 62
FIGURE 28. CircuitSchematic for the 13-2 adder/compressor using 3-2 adders 64
FIGURE 29. Worstcase path simulations ofthe 13-2 adder 65
FIGURE 30. Ripple adder configuration 66
FIGURE 31. ManchesterAdderConfiguration 67
FIGURE 32. Simple I-stage representation ofacarry-skip adder 68
FIGURE 33. Blockdiagram ofapinary reduction carry-lookahead adder tree 70
v
FIGURE 34. Representation ofonestage ofacarry-selectadder 71
FIGURE 35. CircuitSchematicfor one 5-bitaddercellin the fast adder 74
FIGURE 36. Top-Levelcircuitschematic for the 74-bitfast adder 75
FIGURE 37. Simulationsofthe worstcase path inthe fast adder , 76
FIGURE 38. Top levelcircuitschematic ofthe leading 011 detector 80
FIGURE 39. Circuitschematic for one ten-bitsection ofthe leading011 detector 81
FIGURE40. Circuitschematic ofthe five-bit leading011 predictorlogic 82
FIGURE41. Simulationsofthe worstcase path for the leading011 detector and the
shifter 83
FIGURE 42. Simulations ofthe worstcase path for the174bitshifter, includingROM
controller 86
vi
List of Tables
TABLE 1. Second Order Booth Recoder 12
TABLE 2: Entire Partial ProductSummingTree for a25 to 13 Booth Recoded
Multiply 14
TABLE 3. PartialProductAddition with no shifting ;.: 15
TABLE4. Partial ProductAddition with shifting 15
TABLES. Partial ProductAddition ofall zeros : 17
"
TABLE 6. Accumulator addition ofpositive ornegative number 38
TABLE7. Finalsign Determination 39
TABLE 8. Propagation delay ofany inputto the sum and carry outputofthe full
adder 45
TABLE9. Propagation delay ofthe carry inputto the carry output ofthe full adder.45
TABLE 10. Propagation delay ofany inputto the outputofthe 13 to 2compressor 63
TABLE 11. Worstcase propagation delay through the 74 bitadder 73
TABLE 12. Worstcase propagation delay through the Leading 0/1 Detector 79
TABLE 13. Worstcase propagation delay through the 74 bitshifter 85
vii
Abstract
This thesis describes the design of a fully functional 32-Bit Floating Point Multiply/
Accumulator that accepts two 32-bit floating point single basic IEEE format
operands and generates a 32-bit IEEE format result. The two operands are
multiplied together and then summed with an internal accumulation register. The
main objective of this design is to use only one final adder and one rounder block
.to add the partial product terms and the accumulatorterm and still comply with the
IEEE Floating Point Standard 754. The fused multiplication with addition allows
one-cycle throughput with only one rounding error and executes the multiply/
accumulate operation as one indivisible operation. Other features of this design
are the four IEEE rounding modes, round-to-nearest, round-to-positive-infinity,
round-to-negative-infinity, round-to-zero, and four accumulation modes, (A+B), (A
S), (-A+B), -(A+B), where A is the product term and B is the accumulator term.
The thesis presents the system level description to transistor-level .. circuit
schematics and simulations of the multiplier/accumulator. A description of the
IEEE standard is presented for reference. Next, the architectural/functional level
description of the design is examined in detail. A "e-Ievel" programming model
was developed to implement the function and study design trade-ofts. Finally, the
circuit implementation is described with transistor-level, "Spice-like", simulation
shown fdr the critical circuit block implementations. The greatest emphasis is on
the array multiplication and incorporation of the accumulator into the partial
product adder tree.