Design and Evaluation of an Ultra-Low Power Successive Approximation ADC PDF
Preview Design and Evaluation of an Ultra-Low Power Successive Approximation ADC
Design and Evaluation of an Ultra-Low Power Successive Approximation ADC Master thesis performed in Electronic Devices by Dai Zhang Report number: LiTH-ISY-EX--09/4176--SE Linköping Date: March 2009 Design and Evaluation of an Ultra-Low Power Successive Approximation ADC Master thesis in Electronic Devices Dept. of Electrical Engineering at Linköping Institute of Technology by Dai Zhang LiTH-ISY-EX--09/4176--SE Supervisor: Professor Atila Alvandpour Linköpings Universitet Examiner: Professor Atila Alvandpour Linköpings Universitet Linköping, March 2009 Presentation Date Department and Division 2009-03-20 Department of Electrical Engineering Publishing Date (Electronic version) Electronic Devices 2009-03-27 Language Type of Publication ISBN (Licentiate thesis) (cid:57) English Licentiate thesis ISRN: LiTH-ISY-EX--09/4176--SE Other (specify below) (cid:57) Degree thesis Thesis C-level Title of series (Licentiate thesis) Thesis D-level Report Number of Pages Other (specify below) Series number/ISSN (Licentiate thesis) 70 URL, Electronic Version http://www.ep.liu.se Publication Title Design and Evaluation of an Ultra-Low Power Successive Approximation ADC Author(s) Dai Zhang Abstract Analog-to-digital converters (ADC) targeted for use in medical implant devices serve an important role as the interface between analog signal and digital processing system. Usually, low power consumption is required for a long battery lifetime. In such application which requires low power consumption and moderate speed and resolution, one of the most prevalently used ADC architectures is the successive approximation register (SAR) ADC. This thesis presents a design of an ultra-low power 9-bit SAR ADC in 0.13µm CMOS technology. Based on a literature review of SAR ADC design, the proposed SAR ADC combines a capacitive DAC with S/H circuit, uses a binary-weighted capacitor array for the DAC and utilizes a dynamic latch comparator. Evaluation results show that at a supply voltage of 1.2V and an output rate of 1kS/s, the SAR ADC performs a total power consumption of 103nW and a signal-to-noise-and-distortion ratio of 54.4dB. Proper performance is achieved down to a supply voltage of 0.45V, with a power consumption of 16nW. Keywords Analog-to-digital converter (ADC), charge redistribution, CMOS, low power, low supply voltage, successive approximation, latched comparator. Abstract Analog-to-digital converters (ADC) targeted for use in medical implant devices serve an important role as the interface between analog signal and digital processing system. Usually, low power consumption is required for a long battery lifetime. In such application which requires low power consumption and moderate speed and resolution, one of the most prevalently used ADC architectures is the successive approximation register (SAR) ADC. This thesis presents a design of an ultra-low power 9-bit SAR ADC in 0.13µm CMOS technology. Based on a literature review of SAR ADC design, the proposed SAR ADC combines a capacitive DAC with S/H circuit, uses a binary-weighted capacitor array for the DAC and utilizes a dynamic latch comparator. Evaluation results show that at a supply voltage of 1.2V and an output rate of 1kS/s, the SAR ADC performs a total power consumption of 103nW and a signal-to-noise-and-distortion ratio of 54.4dB. Proper performance is achieved down to a supply voltage of 0.45V, with a power consumption of 16nW. Keywords: Analog-to-digital converter (ADC), charge redistribution, CMOS, low power, low supply voltage, successive approximation, latched comparator. III Acknowledgement First of all, I would like to express my sincere gratitude to Professor Atila Alvandpour, who introduced the topic and supervised this thesis. It was really a very interesting topic! Valuable discussions with him not only make my thesis progress smoothly but also encourage me to think more professionally in the field of research. I would like to thank PhD students in the division of electronic devices for their kind help and open discussions: Timmy Sundström, Jonas Fritzin and Behzad Mesgarzadeh. I would like to thank Arta Alvandpour for research support and Anna Folkeson for administrative issues. I would like to thank all the friends, especially to my close friends: Bao, Yuexian and Fang for the precious time we shared and will be shared. Finally, deepest thanks go to my mother and grandparents. This thesis is dedicated to them. IV
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