A New Family of CMOS Cascode-Free Amplifiers with High Energy-Efficiency and Improved Gain PDF
Preview A New Family of CMOS Cascode-Free Amplifiers with High Energy-Efficiency and Improved Gain
Ricardo Filipe Sereno Póvoa João Carlos da Palma Goes Nuno Cavaco Gomes Horta A New Family of CMOS Cascode-Free Amplifi ers with High Energy-Effi ciency and Improved Gain fi A New Family of CMOS Cascode-Free Ampli ers fi with High Energy-Ef ciency and Improved Gain Ricardo Filipe Sereno Póvoa João Carlos da Palma Goes Nuno Cavaco Gomes Horta A New Family of CMOS fi Cascode-Free Ampli ers fi with High Energy-Ef ciency and Improved Gain RicardoFilipeSerenoPóvoa JoãoCarlosdaPalmaGoes InstitutodeTelecomunicações UNINOVA,FaculdadedeCiênciase InstitutoSuperiorTécnico Tecnologia,UniversidadeNovadeLisboa UniversidadedeLisboa Lisboa,Portugal Lisboa,Portugal NunoCavacoGomesHorta InstitutodeTelecomunicações InstitutoSuperiorTécnico UniversidadedeLisboa Lisboa,Portugal ISBN978-3-319-95206-2 ISBN978-3-319-95207-9 (eBook) https://doi.org/10.1007/978-3-319-95207-9 LibraryofCongressControlNumber:2018951770 ©SpringerInternationalPublishingAG,partofSpringerNature2019 Thisworkissubjecttocopyright.AllrightsarereservedbythePublisher,whetherthewholeorpart of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation,broadcasting,reproductiononmicrofilmsorinanyotherphysicalway,andtransmissionor informationstorageandretrieval,electronicadaptation,computersoftware,orbysimilarordissimilar methodologynowknownorhereafterdeveloped. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt fromtherelevantprotectivelawsandregulationsandthereforefreeforgeneraluse. Thepublisher,theauthors,andtheeditorsaresafetoassumethattheadviceandinformationinthisbook arebelievedtobetrueandaccurateatthedateofpublication.Neitherthepublishernortheauthorsorthe editorsgiveawarranty,expressorimplied,withrespecttothematerialcontainedhereinorforanyerrors oromissionsthatmayhavebeenmade.Thepublisherremainsneutralwithregardtojurisdictionalclaims inpublishedmapsandinstitutionalaffiliations. ThisSpringerimprintispublishedbytheregisteredcompanySpringerNatureSwitzerlandAG Theregisteredcompanyaddressis:Gewerbestrasse11,6330Cham,Switzerland Ricardo Póvoa TomydearMarta,foreverythingthatisworth fighting for. João Goes To Valentim and Madalena. Nuno Horta To Carla, João, and Tiago. Preface Amplifiers are important in several electronic systems and processing chains, e.g., radio-frequency transceivers in wireless networks, data acquisition channels, or analog-to-digitalconverters(ADCs).Therefore,theapplicationsofamplifiersspread fromanalogtomixed-signaldesign.Desirably,amplifiersallowanefficientampli- ficationofsmall-signals,withoutaddingsignificantnoisetothechain,andcanalso operateassignalcomparatorsinADCs.Thepowerreductionnecessity,theintrinsic gain reduction and high variability, with the low-supply voltage trend of modern CMOS technologies, has driven the evermore challenging design of amplifiers to implement multiple gain stages and possibly one output driver stage. Regarding single-stage amplifiers, commonly more power efficient, high gains are normally achievedusingcascodedevicesorcascadedstages.However,thisleadstoreduced output swings (OS) due to the lower supply voltages in hand with the stacking of devices. In residue amplifiers, inside ADCs, one possible solution is dynamic amplification. Dynamic CMOS amplifiers are proposed by Copeland and Rabaey, in1979,inwhichtheideaisthatthebiascurrentisnotconstantbutchangedduring amplification.Thispropertyisimportant,particularlyinswitched-capacitorcircuits, where the amplifier can be biased in strong inversion with a large current in the beginning and then continuously reduced the current toward weak inversion, until the power is practically cut off, maximizing both the gain and the OS of the amplifier. This work addresses the need for energy-efficient amplifiers and gain enhancement strategies, compatible with lower supply voltages, by proposing a completenewfamilyofsingle-stagecascode-freeamplifiers,withdesign,optimiza- tion, and experimental evaluation. The energy efficiency and topological potential aremaximizedthroughadvancedautomationcarriedbyAIDA,ananalogICdesign and optimization framework, based on computational intelligence. The topologies are proposed using the UMC 130 nm CMOS technology for proof of concept: voltage combiners (VC) biased operational transconductance amplifier (OTA), VC biasedOTAwithcurrentstarvingforhighergainandenergyefficiency,foldedVC biased OTA for lower-voltage sources, and a dynamic VC biased OTA targeting ADCs,withgainsabove50dBandenergy-efficientfigure-of-meritvaluesof1024, vii viii Preface 1102, 2279, and 1349 MHz (cid:1) pF/mA, correspondingly. The presented results are beyond what is achievable with a classic folded-cascode amplifier, and, regarding dynamicamplifiers,theproposedsolutionsclearlycontributetoadvancesinthestate of the art. This work is organized in six chapters. Chapter 1 presents a brief introductionwiththemotivationandcontexttodevelopandproposenewamplifier topologies, with high energy efficiency and gain improvement, particularly in the environmentoftheInternetofThings,emphasizingthewidefieldofapplicationsof amplifiers.Chapter2discussesthebackgroundandthestateoftheartofsingle-stage amplifiers, providing the context of the developed work. The main topologies are detailed: the telescopic-cascode, the mirrored-cascode, and the folded-cascode amplifiers, followed by the recycling folded-cascode amplifier with the corresponding improvements and surveying the concept of dynamic amplification inCMOStechnologies.Theperformancemetricsaresummarized,andathroughout comparisonofthepriorartisprovided.Chapter3presentsthearchitecturesproposed in this work and shows circuit implementations in detail. The basic voltage-com- binerstructureispresentedanddetailedbothatanalyticalandsimulationlevels.The complete set of amplifiers is shown, both in terms of topological description and analytic analysis. Sizing strategies and initial designs, i.e., first approaches that guaranteefunctionalcircuits,arepresentedwithresultsatsimulationlevel,validat- ing the proposed topologies with applied noise modeling. Chapter 4 presents the optimizationframework,AIDA;thecompletesetupfortheoptimization,regarding the objectives, specifications, variables, and ranges; and post-optimization simula- tion results for selected sizing solutions, positioning the proposed circuits in the context of the state of the art of single-stage amplifiers. Chapter 5 presents the printed circuit board developed to properly measure the fabricated circuits during thecourseofthepresentdissertation.Theprototypedsolutionsaredetailed:layout, post-layout,MonteCarlosimulations,experimentalmeasurements,andcomparison withthestateoftheart.Finally,Chapter6drawstheconclusions,compoundedwith a summary of all the achieved developments, positioning the proposed topologies relativetothestateoftheartofsingle-stageamplificationarchitectures. Lisboa,Portugal RicardoFilipeSerenoPóvoa JoãoCarlosdaPalmaGoes NunoCavacoGomesHorta Acknowledgments If one considers a short-term signal in frequency, one knows that it extends inten- sively in time. The same principle applies to the expression of our gratitude to the followingwonderfulhumanbeings,towhomwededicatethiswork. Ricardo Póvoa would like to thank his family for all the long-term love and support; his closest friends, David Raposo, Inês Vitorino, João Doroana, João S. Braz, Luís Cruz, Luís Pinto, Marta Taveira, Patrícia Madeira, Rafael Cabral, Rafaela S. Braz, and Vitor Camacho; Prof. Doutor Nuno Cavaco Gomes HortaandProf.DoutorJoãoCarlosdaPalmaGoes,foralltheconfidence,enthusi- asm,andguidancethroughoutthedevelopmentofthiswork;hisfriendsandcolleges fromInstitutoSuperiorTécnicoandInstitutodeTelecomunicações,NunoLourenço, Ricardo Martins, António Canelas, Mauro Santos, Marco Pereira, and Mario Assunção; and the expert advices from Prof. Doutor João M. Vaz, Prof. Doutor JorgeM.Guilherme,Prof.DoutorJorgeM.Fernandes,andProf.DoutorMarcelino B.Santos. Finally,theauthorswouldliketoexpresstheirgratitudeforthefinancialsupport thatmadethisworkpossible.ThisworkwassupportedinpartbyFundaçãoparaa Ciência e Tecnologia (Grant FCT SFRH/BD/133662/2017) and by Instituto de Telecomunicações(ResearchProjectRAPIDUID/EEA/50008/2013). ix Contents 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 BackgroundandStateoftheArt. . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 BackgroundandInitialConsiderations. . . . . . . . . . . . . . . . . . . . . 7 2.2 OverviewonAmplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.1 OperationalAmplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.2 Single-StageAmplifiers. . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 PerformanceMetricsofAmplifiers. . .. . . .. . . .. . . .. . . .. . . .. 15 2.3.1 GainandGain-BandwidthProduct. . . . . . . . . . . . . . . . . 15 2.3.2 FigureofMerit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.3 Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.4 Common-ModeRejectionRatio. . . . . . . . . . . . . . . . . . . 16 2.3.5 PowerSupplyRejectionRatio. . . . . . . . . . . . . . . . . . . . 17 2.3.6 SlewRate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.7 SettlingTime. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.8 OffsetVoltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.9 OutputVoltageSwing. . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.10 StabilityandFrequencyCompensation. . . . . . . . . . . . . . 20 2.4 OperationalTransconductanceAmplifiers. . . . . . . . . . . . . . . . . . . 22 2.5 TheCascodeAmplifierTopologies. . . . . . . . . . . . . . . . . . . . . . . 24 2.5.1 BasicCascodeStages. . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.5.2 Telescopic-CascodeAmplifier.. . .. . . .. . . .. . . .. . . .. 27 2.5.3 Mirrored-CascodeAmplifier. . . . . . . . . . . . . . . . . . . . . . 29 2.5.4 Folded-CascodeAmplifier. . . . . . . . . . . . . . . . . . . . . . . 30 2.5.5 GainEnhancementTechniquesfortheCascode Architectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.6 TheRecyclingFolded-CascodeAmplifier. . . . . . . . . . . . . . . . . . 35 2.7 DynamicCMOSAmplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.8 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 xi xii Contents 3 ProposedFamilyofCMOSAmplifiers. . . . . . . . . . . . . . . . . . . . . . . 45 3.1 Voltage-CombinerStructure. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2 Voltage-Combiner-BiasedOTA. . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.3 Voltage-Combiner-BiasedOTAwithCurrentStarving. . . . . . . . . 57 3.4 FoldedVoltage-Combiner-BiasedOTA. . . . . . . . . . . . . . . . . . . . 61 3.5 DynamicVoltage-Combiner-BiasedOTA. . .. . . . .. . . . .. . . . .. 65 3.6 NoiseModeling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.6.1 NoiseDefinition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.6.2 NoiseTypes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.6.3 GenericModeling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.6.4 Voltage-CombinerNoiseModeling. . . . . . . . . . . . . . . . . 79 3.7 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4 DesignOptimizationandResults.. . . . . . . . .. . . . . . . .. . . . . . . .. . 85 4.1 OptimizationFramework. . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . 85 4.2 Voltage-CombinerBiasedOTA. . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.3 Voltage-CombinerBiasedOTAwithCurrentStarving. . . . . . . . . 90 4.4 FoldedVoltage-CombinerBiasedOTA. . . . . . . . . . . . . . . . . . . . 91 4.5 DynamicVoltage-CombinerBiasedOTA. . . . . . . . . . . . . . . . . . . 95 4.6 EDATechniquesinOrganicTFTTechnologies. . . . . . . . . . . . . . 101 4.6.1 ContextofOrganicTechnology. . . . . . . . . . . . . . . . . . . 102 4.6.2 OptimizationSetup. . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4.6.3 OptimizationResults. . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.6.4 YieldOptimizationProcess. . . . . . . . . . . . . . . . . . . . . . 108 4.7 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5 IntegratedPrototypesandExperimentalEvaluation. . . . . . . . . . . . . 115 5.1 TestPrintedCircuitBoard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 5.2 Voltage-Combiner-BiasedOTA. . . . . . . . . . . . . . . . . . . . . . . . . . 116 5.3 Voltage-Combiner-BiasedOTAwithCurrentStarving. . . . . . . . . 122 5.4 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6 ConclusionsandFutureProspects.. . . . .. . . . .. . . . .. . . . .. . . . .. 133 Biographies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
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